Patents by Inventor Brian Moane

Brian Moane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8791674
    Abstract: A voltage regulator receives an unregulated DC input voltage supply and provides a regulated DC output voltage. A primary pass element and an external resistor are located in a primary current path through which a load current flows from the input terminal to the output terminal. The voltage regulator includes two control circuits that control the impedances of two pass elements. Power dissipation can be improved and the dropout voltage can be reduced by maintaining the voltage on an internal node of the voltage regulator.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 29, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Brian Moane
  • Patent number: 8680620
    Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 25, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Javier A Salcedo, Michael Lynch, Brian Moane
  • Publication number: 20130032882
    Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Michael Lynch, Brian Moane
  • Publication number: 20120013320
    Abstract: A voltage regulator receives an unregulated DC input voltage supply and provides a regulated DC output voltage. A primary pass element and an external resistor are located in a primary current path through which a load current flows from the input terminal to the output terminal. The voltage regulator includes two control circuits that control the impedances of two pass elements. Power dissipation can be improved and the dropout voltage can be reduced by maintaining the voltage on an internal node of the voltage regulator.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: Analog Devices, Inc.
    Inventor: Brian Moane
  • Publication number: 20070159219
    Abstract: An output stage interface circuit (50) implemented on a P-substrate comprises a first substrate diffusion isolated main NMOS transistor (MN1) coupling a data output terminal (5) to a first rail (2) which is held at ground, and a second main PMOS transistor MP2 coupling the data output terminal (5) to a second rail (3) to which the power supply voltage VDD is applied. First and second data control signals on first and second data control lines (8) and (9) through first and second primary and secondary buffer circuits (11, 14, 12, 15) selectively operate the first main transistor MN1 and the second main transistor MP2 for determining the logic high and low states of the data output terminal (5).
    Type: Application
    Filed: October 27, 2006
    Publication date: July 12, 2007
    Applicant: Analog Devices, Inc.
    Inventors: Colm Ronan, John Twomey, Brian Moane, Liam White