Abstract: An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.

Abstract: A processor configuration for processing multi-precision shift instructions is provided. The multi-precision shift instructions are executed following a previous shift instruction of the same increment, such as a logical or arithmetic left or right shift operation. The first shift instruction shifts a first memory word by the shift increment and stores this shifted value into memory. The second, and any subsequent, multi-precision shift instruction shifts the next memory word by the shift increment and concatenates the bits shifted out of the previously shifted memory word into bit positions of the memory word presently being shifted. This concatenated value is then stored back to memory and forms another part of the multi-precision shifted value.

Abstract: A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.

Abstract: A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.