Abstract: A system for providing ephemeral keys for a cryptographic system includes a secure enclave configured to generate one or more ephemeral keys (EKs), where each EK of the one or more EKs has a lifetime associated with the respective EK, and one or more secured devices connected to the secure enclave, where each secured device of the one or more secured devices has a trusted platform module (TPM) configured to acquire at least one of the one or more EKs, where the TPM of each secured device further is configured to generate secured data in response to validating the lifetime of an associated EK by encrypting sensitive data with the associated EK, and where each secured device of the one or more secured devices is further configured to transmit the secured data to an entity external to the secured device.

Abstract: In general, one aspect disclosed features an apparatus comprising: a receiver comprising a receiver inductor-capacitor (LC) tank; a transmitter comprising an oscillator; and a capacitive isolation barrier electrically coupled between an output of the transmitter and an input of the receiver.

Abstract: The present disclosure relates to a pharmaceutical combination comprising (a) a histone deacetylase 6 inhibitor and (b) an aurora kinase inhibitor, including combined preparations and pharmaceutical compositions thereof; uses of such combination in the treatment or prevention of cancer; and methods of treating or preventing cancer in a subject comprising administering a therapeutically effective amount of such combination.

Abstract: The present disclosure relates to a pharmaceutical combination comprising (a) a histone deacetylase 6 inhibitor and (b) an aurora kinase inhibitor, including combined preparations and pharmaceutical compositions thereof; uses of such combination in the treatment or prevention of cancer; and methods of treating or preventing cancer in a subject comprising administering a therapeutically effective amount of such combination.

Abstract: The present disclosure relates to a pharmaceutical combination comprising (a) a histone deacetylase 6 inhibitor and (b) an aurora kinase inhibitor, including combined preparations and pharmaceutical compositions thereof; uses of such combination in the treatment or prevention of cancer; and methods of treating or preventing cancer in a subject comprising administering a therapeutically effective amount of such combination.

Abstract: Adaptive on-time switching voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator comprises: a switching circuit configured to generate a switching signal at a switching node according to a pulse-width modulated (PWM) signal; a phase-lock loop (PLL) configured to lock the PWM signal to a clock reference signal, the PLL comprising: a PWM signal generator configured to generate the PWM signal according to an error signal, and a phase detector configured to generate the error signal based on the PWM signal and the clock reference signal.

Abstract: Adaptive on-time switching voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator comprises: a switching circuit configured to generate a switching signal at a switching node according to a pulse-width modulated (PWM) signal; a phase-lock loop (PLL) configured to lock the PWM signal to a clock reference signal, the PLL comprising: a PWM signal generator configured to generate the PWM signal according to an error signal, and a phase detector configured to generate the error signal based on the PWM signal and the clock reference signal.

Abstract: The present disclosure relates to a pharmaceutical combination comprising (a) a histone deacetylase 6 inhibitor and (b) an aurora kinase inhibitor, including combined preparations and pharmaceutical compositions thereof; uses of such combination in the treatment or prevention of cancer; and methods of treating or preventing cancer in a subject comprising administering a therapeutically effective amount of such combination.

Abstract: A switch-mode DC converter configured to generate a converted voltage from an input voltage is provided. The switch-mode DC converter includes an inductor configured to store energy, and a switch coupled with the inductor at a switching node, wherein the switch is configurable to be turned on or off to control the discharging of the energy stored at the inductor to an output node of the converter, wherein the output node is configured to provide the converted voltage. The switch-mode DC converter also includes a circuit configured to control a timing of turning-off of the switch based on a voltage difference between the switch, wherein a measurement of the voltage difference is adjusted based on a voltage at the switching node.

Abstract: A switch-mode DC converter configured to generate a converted voltage from an input voltage is provided. The switch-mode DC converter includes an inductor configured to store energy, and a switch coupled with the inductor at a switching node, wherein the switch is configurable to be turned on or off to control the discharging of the energy stored at the inductor to an output node of the converter, wherein the output node is configured to provide the converted voltage. The switch-mode DC converter also includes a circuit configured to control a timing of turning-off of the switch based on a voltage difference between the switch, wherein a measurement of the voltage difference is adjusted based on a voltage at the switching node.

Abstract: A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for transmission over the serial interface between a master device and at least one slave device. Upon receipt of the control word at the at least one slave device, the preamble is detected by the slave device. Upon detection of the preamble, the slave device is enabled to respond to information within the control word as appropriate.

Abstract: The present invention provides methods for identifying agents that modulate a level or an activity of a mitochondrial NAD-dependent deacetylase polypeptide, as well as agents identified by the methods. The invention further provides methods of modulating mitochondrial NAD-dependent deacetylase activity in a cell. The invention further provides methods of modulating mitochondrial function by modulating the activity of mitochondrial NAD-dependent deacetylase.

Abstract: An improved Class G type amplifier which switches between multiple power rails depending upon the instantaneous amplitude of the input signal versus the power rails. The low voltage (inner) amplifier includes a plurality of parallel amplifier devices, and the high voltage (outer) amplifier includes a plurality of parallel amplifier devices. A plurality of switches each couples the input signal to either a respective one of the inner amplifier devices or a respective one of the outer amplifier devices. The switches are activated sequentially, such that the switching from inner to outer amplifier devices or vice versa is staggered over some period of time. This avoids having a single, large glitch in the output, and spreads multiple smaller glitches over enough time that some of the glitch energy can fall within the frequency range where the amplifier's feedback circuitry can eliminate its noise. The switches are sequentially activated by a series of delay elements.

Abstract: A phase-slipping phase-locked loop which generates an output signal whose frequency is a non-integer multiple of a reference frequency. The PLL has a first input for receiving a first binary value i which specifies an integer portion of the frequency multiplier, and a second input for receiving a second binary value f which specifies a fractional portion of the frequency multiplier. A multi-phase VCO has a plurality v of outputs on equal phase shifted spacing. The phase slipping is applied every i cycles, and the second binary value f specifies a phase slip stride, such that the frequency multiplier equals i+f/v.

Abstract: An audio amplifier such as for driving headphones. The amplifier includes multiple amplifier devices coupled in parallel. Both a bias generator and a volume control are responsive to a user setting. Under low output signal conditions, one or more of the amplifier devices are disabled in response to the user setting. Disabled amplifier devices do not consume output bias current. Thus the audio amplifier has reduced power consumption, and the system has longer battery life.

Abstract: An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: Current output stages are provided. In accordance with an embodiment, a current output stage includes a voltage follower circuit, a first current mirror and a second current mirror. A node of the voltage follower circuit provides a voltage that follows a voltage at the output of the current output stage. An input of the first current mirror is connected (e.g., by a current path of a transistor) to the node of the voltage follower circuit that follows the voltage at the output of the current output stage. An output of the first current mirror is connected to an input of the second current mirror. An output of the second current mirror is connected to the input of the current output stage.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.

Abstract: Circuits and methods for coherent noise cancellation are provided. More specifically, circuits and methods are provided for coherent cancellation of noise that is present in a data signal due to noise being present in the source signal (e.g., an optical signal) that is used to produce the data signal. The circuits, which use a subtraction process rather than division, are easy to implement in a chip, and provide for wide bandwidth performance.