Patents by Inventor Brian P. Callaway
Brian P. Callaway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816357Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.Type: GrantFiled: August 12, 2021Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, Brian P. Callaway
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Patent number: 11804257Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.Type: GrantFiled: November 22, 2022Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, Brian P. Callaway
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Patent number: 11721385Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.Type: GrantFiled: August 12, 2021Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, Brian P. Callaway
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Publication number: 20230090919Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.Type: ApplicationFiled: November 22, 2022Publication date: March 23, 2023Inventors: Anthony D. Veches, Brian P. Callaway
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Publication number: 20230046912Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Anthony D. Veches, Brian P. Callaway
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Publication number: 20230048317Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Anthony D. Veches, Brian P. Callaway
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Patent number: 11532349Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.Type: GrantFiled: April 2, 2021Date of Patent: December 20, 2022Assignee: Micron Technology, Inc.Inventors: Anthony D. Veches, Brian P. Callaway
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Patent number: 11488651Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.Type: GrantFiled: December 28, 2020Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
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Publication number: 20220319569Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.Type: ApplicationFiled: April 2, 2021Publication date: October 6, 2022Inventors: Anthony D. Veches, Brian P. Callaway
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Patent number: 11361808Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: October 15, 2018Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Patent number: 11264075Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: October 15, 2018Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20210118490Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
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Patent number: 10930335Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: December 21, 2018Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Patent number: 10885967Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.Type: GrantFiled: January 14, 2019Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
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Publication number: 20200227113Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.Type: ApplicationFiled: January 14, 2019Publication date: July 16, 2020Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
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Publication number: 20190130961Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may he configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: December 21, 2018Publication date: May 2, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20190051344Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: DEBRA M. BELL, Jeff A. McClain, Brian P. Callaway
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Patent number: 10134461Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: May 8, 2015Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
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Publication number: 20150243339Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Inventors: DEBRA M. BELL, Jeff A. McClain, Brian P. Callaway
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Patent number: 9047978Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.Type: GrantFiled: August 26, 2013Date of Patent: June 2, 2015Assignee: Micron Technology, Inc.Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway