Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Abstract: A method and system for applying run rules on an individual part number basis in order to detect out-of-control events for a distinct sub-population within a general technology population. The invention thus provides for line tailoring by part number by acquiring measurement data of the part number from a manufacturing line for a measured parameter; retrieving a specification for the part number from a database; executing custom run rules by part number against the measured data using the specifications; and rejecting requests to process the part number if a run rule violation exists.

Abstract: An intergrated closed apparatus and system for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate. The apparatus and system include a heating chamber for heating the contaminated substrate to an elevated temperature, and an input line for purging the chamber with a chlorine-containing gas. The chlorine dissociates from the chlorine-containing gas, reacts with the contaminates, and forms volatile chloride byproducts which are removed from the heating chamber via an output line. A cooling chamber of the apparatus and system having an input line for providing a gas therein cools the substrate. A workpiece holds the substrate, which in turn, is held in position by a pedestal. The pedestal is in contact with a door that seals the closed apparatus and system, whereby the door transfers the substrate from the heating chamber to the cooling chamber, and vice versa.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: A method and system for applying run rules on an individual part number basis in order to detect out-of-control events for a distinct sub-population within a general technology population. The invention thus provides for line tailoring by part number by acquiring measurement data of the part number from a manufacturing line for a measured parameter; retrieving a specification for the part number from a database; executing custom run rules by part number against the measured data using the specifications; and rejecting requests to process the part number if a run rule violation exists.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminants on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminants on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.