Patents by Inventor Brian P. Downey

Brian P. Downey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283597
    Abstract: A semiconductor device structure including a scandium (Sc)- or yttrium (Y)-containing material layer situated between a substrate and one or more overlying layers. The Sc- or Y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the Sc- or Y-containing material layer. The Sc- or Y-containing material layer can be grown within an epitaxial group III-nitride device structure for applications such as electronics, optoelectronics, and acoustoelectronics, and can improve the etch-depth accuracy, reproducibility and uniformity.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 7, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew T. Hardy, Brian P. Downey, David J. Meyer
  • Patent number: 10262856
    Abstract: Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey, Daniel S. Green
  • Publication number: 20180174833
    Abstract: Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 21, 2018
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey, Daniel S. Green
  • Publication number: 20180130883
    Abstract: A semiconductor device structure including a scandium (Sc)- or yttrium (Y)-containing material layer situated between a substrate and one or more overlying layers. The Sc- or Y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the Sc- or Y-containing material layer. The Sc- or Y-containing material layer can be grown within an epitaxial group III-nitride device structure for applications such as electronics, optoelectronics, and acoustoelectronics, and can improve the etch-depth accuracy, reproducibility and uniformity.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 10, 2018
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew T. Hardy, Brian P. Downey, David J. Meyer
  • Patent number: 9876081
    Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: January 23, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey
  • Patent number: 9656859
    Abstract: A process for fabricating a suspended microelectromechanical system (MEMS) structure comprising epitaxial semiconductor functional layers that are partially or completely suspended over a substrate. A sacrificial release layer and a functional device layer are formed on a substrate. The functional device layer is etched to form windows in the functional device layer defining an outline of a suspended MEMS device to be formed from the functional device layer. The sacrificial release layer is then etched with a selective release etchant to remove the sacrificial release layer underneath the functional layer in the area defined by the windows to form the suspended MEMS structure.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 23, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey
  • Publication number: 20160304340
    Abstract: A process for fabricating a suspended microelectromechanical system (MEMS) structure comprising epitaxial semiconductor functional layers that are partially or completely suspended over a substrate. A sacrificial release layer and a functional device layer are formed on a substrate. The functional device layer is etched to form windows in the functional device layer defining an outline of a suspended MEMS device to be formed from the functional device layer. The sacrificial release layer is then etched with a selective release etchant to remove the sacrificial release layer underneath the functional layer in the area defined by the windows to form the suspended MEMS structure.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey
  • Publication number: 20160035851
    Abstract: A method for integrating epitaxial, metallic transition metal nitride (TMN) layers within a compound semiconductor device structure. The TMN layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (SiC) and the Group III-Nitrides (III-Ns) such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their various alloys. Additionally, the TMN layers have excellent thermal stability and can be deposited in situ with other semiconductor materials, allowing the TMN layers to be buried within the semiconductor device structure to create semiconductor/metal/semiconductor heterostructures and superlattices.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 4, 2016
    Inventors: David J. Meyer, Brian P. Downey, Douglas S. Katzer
  • Publication number: 20150021624
    Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: David J. Meyer, Brian P. Downey