Abstract: To validate an integrated circuit (IC), the IC is imaged by scanning an optical beam over the IC to optically inject carriers and measuring an output signal generated by the IC in response to the injected optical carriers. A comparison between the image of the IC and a reference image is computed, and suspect regions of the IC are identified based on the comparison. The reference image may be an image of a reference IC. In another approach, images of training ICs are acquired, and a deep learning algorithm is trained to transform corresponding training IC layouts to the images of the training ICs. The trained deep learning algorithm then transforms a layout of the IC to generate the reference image. The comparison may be computed by computing an error metric for each region corresponding to a standard cell in the reference image.

Abstract: A wide-band digital buffer formed in a III-V substrate including a first transistor, a second transistor, a pull-up circuit shifts a t signal to a level of the first transistor. A first capacitor receives the signal, and passes at least a portion of the AC component of the signal to the first transistor. A resistor receives a first bias voltage, and passes it to the first transistor. A pull-down circuit shifts a second signal to a level of the second transistor. A second capacitor receives the second signal, and passes at least a portion of the AC component of the second signal to the second transistor. A second resistor receives a second bias voltage, and passes it to the second transistor.