Patents by Inventor Brian P. Moran

Brian P. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150234726
    Abstract: Techniques and mechanisms to exchange communications via a printed circuit board (PCB) between a processor device and a memory device. In an embodiment, the processor device is configured based on a memory type of the memory device to an interface mode of multiple interface modes each corresponding to a different respective one of multiple memory standards. A voltage regulator (VR) is programmed, based on the memory type, to a VR mode to provide one or more voltages to the memory device via a hardware interface on the PCB. In another embodiment, x signal lines of an interconnect disposed in or on the PCB are each coupled between the processor device and the memory device to one another. The value x is an integer equal to a total number of signals of a superset of sets of signals each specified by a different respective one of the multiple memory standards.
    Type: Application
    Filed: December 19, 2014
    Publication date: August 20, 2015
    Inventors: Brian P. Moran, Konika Ganguly, Rebecca Z. Loop, Xiang Li, Christopher E. Cox
  • Patent number: 4616259
    Abstract: In cases where the reference signal pulses supplied to one input of the phase detector of a phase-locked loop (PLL) may shift in phase significantly, the PLL may not be able to lock-in quickly enough to the apparent input pulse frequency change. In video monitor circuits where digital counters are clocked by the output frequency of the PLL, for example, the momentary loss of synchronism can cause horizontal scanning of the monitor screen to start too early or too late. A circuit is provided that lets the PLL make normal phase and frequency adjustments during a predetermined period during which counter reset is disabled. The circuit provides a window before and after this period during which counter reset is enabled. A reference pulse with a substantial phase error falls within the window. If three conditions are met, namely, the Reset Enable window exists, the reference pulse occurred within the window and the scan is near the bottom of the monitor screen, then a counter reset to zero signal is produced.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: October 7, 1986
    Assignee: General Electric Company
    Inventors: Brian P. Moran, Edward W. Andrews, Stanford W. Miller
  • Patent number: 4348590
    Abstract: A system for supplying a selected voltage between the anode and cathode of an x-ray tube independent of power source voltage variations couples the x-ray tube power supply to the source with a transformer whose output voltages are selectable with tap switches. Prevailing source voltage and selected applied voltage are sensed and represented by analog signals which are converted to binary digital codes that form addresses for a read-only memory. The read-only memory is programmed with data representative of the pattern in which the tap switches should be set for the transformer to supply the selected voltage at the prevailing source voltage. When addressed by combinations of code words representative of the selected and source voltages, the memory outputs a code word that is used to set the switches in the corresponding pattern.
    Type: Grant
    Filed: October 27, 1980
    Date of Patent: September 7, 1982
    Assignee: General Electric Company
    Inventors: Herbert E. Daniels, Harold E. Stehman, Brian P. Moran