Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Abstract: A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.

Abstract: A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.

Abstract: An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.

Abstract: An approach to introducing adaptive routing into a communication approach for passing messages between nodes over links between the nodes includes forming virtual channels over the links of the system and defining a deterministic routing function over the virtual channels such that the deterministic routing function is deadlock free. Adaptive routing is then permitted at nodes using the existing virtual channels by introducing a constraint on the available virtual channels used to forward communication that arrives at a node for a particular destination. The constraint on the virtual channels is such that the adaptive system is also deadlock free.

Abstract: An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.

Abstract: An approach to introducing adaptive routing into a communication approach for passing messages between nodes over links between the nodes includes forming virtual channels over the links of the system and defining a deterministic routing function over the virtual channels such that the deterministic routing function is deadlock free. Adaptive routing is then permitted at nodes using the existing virtual channels by introducing a constraint on the available virtual channels used to forward communication that arrives at a node for a particular destination. The constraint on the virtual channels is such that the adaptive system is also deadlock free.

Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.

Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.