Abstract: A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

Abstract: A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

Abstract: A differential amplifier and method including a differential pair of input MOS transistors coupled to a common tail current source and a pair of MOS load transistors, with the amplifier outputs being disposed intermediate the input and load transistors. Biasing circuitry is included to maintain the load transistors in the linear region of operation. Reset transistors can be used to periodically reset the amplifier by connecting the outputs directly to the inputs.

Abstract: A buffer circuit having voltage clamping capabilities. The buffer circuit includes an input transistor having a gate which receives the input voltage to be buffered and a source connected to a current source. A first clamping transistor has a source connected to the source of the input transistor and a gate which receives a lower clamping voltage. A second clamping transistor is connected intermediate the input transistor and a power supply rail and has a gate for receiving an upper clamping voltage. In one embodiment, the output of the buffer is at the source of the input transistor. In another embodiment, the buffer is implemented as a differential amplifier with the input, first clamping and second clamping transistors being on an input half of the amplifier and the output of the buffer being at the output half.

Abstract: A sample and hold circuit having a single-ended input and a differential output. Switching circuitry operates to couple first and second input capacitors to the single-ended input and to a reference voltage, respectively, when in a sample mode. The switching circuitry also operates in the sample mode to connect a first pair of feedback capacitors between the inputs and outputs of a differential amplifier and to connect a second pair of capacitors between known reference voltages. During the hold mode, the switching circuitry causes the charge present on the input capacitors to be transferred equally to the second pair of feedback capacitors so that the output of the differential amplifier is a differential representation of the single-ended input.

Abstract: An input switch for use in a switch-capacitor circuit having unified architecture, and a switch-capacitor circuit including such an input switch, an amplifier, a capacitor between the amplifier and switch, and at least one NMOS transistor. The input switch samples an input potential in a sampling mode, receives a reference potential, and includes a transmission gate having a first NMOS transistor. The switch is configured to prevent the transmission gate from passing the reference to the capacitor when the reference is so low that the difference between the sampled input and reference is below an overdrive-causing level, thereby preventing capacitor charge loss which would otherwise lead to overdrive while the switch-capacitor circuit compares the reference with the sampled input.

Abstract: An analog-to-digital converting including a resistor network for producing a group of coarse differential reference voltages and a group of fine differential reference voltages, a bank of coarse comparators receiving the coarse differential reference voltage and a bipolar differential input voltage. A bank of fine comparators receives selected ones of the group of fine differential reference voltages, based upon the output of the coarse comparators during a previous clock interval, and a unipolar differential input voltage derived from the bipolar input. Encoder circuitry converts the output of the coarse and fine comparator banks to a digital output.

Abstract: An analog-to-digital converting including a resistor network for producing a group of coarse differential reference voltages and a group of fine differential reference voltages, a bank of coarse comparators receiving the coarse differential reference voltage and a bipolar differential input voltage. A bank of fine comparators receives selected ones of the group of fine differential reference voltages, based upon the output of the coarse comparators during a previous clock interval, and a unipolar differential input voltage derived from the bipolar input. Encoder circuitry converts the output of the coarse and fine comparator banks to a digital output.

Abstract: An interpolating comparator bank having first and second differential amplifiers, each having a differential input and a differential output and first, second and third comparator circuits, each having differential inputs. The differential output of the first differential amplifier and second differential amplifier are coupled to the first and second comparator inputs, respectively. The differential outputs of the first and second differential amplifiers are also both coupled to the differential input of the second comparator circuit. In analog to digital converter circuit applications, the first and second comparators function to provide outputs indicative of the magnitude of a differential input voltage relative to first and third differential reference voltages produced, for example, by a resistor network.