Patents by Inventor Brian Payton Bowman

Brian Payton Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11347686
    Abstract: An apparatus includes a processor to: instantiate data buffers of a queue, reading threads, and provision threads; within each reading thread, use an identifier provided in a data buffer of the queue to retrieve the corresponding data set part and part metadata from storage device(s), and store both within the data buffer; operate the queue as a (FIFO) buffer; within each provision thread, retrieve a row group from among multiple row groups and corresponding metadata from within the data buffer, use information in the metadata to decompress at least one column, and provide the data values of the row group to the requesting device or an application routine; and in response to each instance of storage of a data set part within a data buffer of the queue, analyze the availability of storage space and/or of processing resources to determine whether to dynamically adjust the quantity of reading threads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 31, 2022
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener
  • Patent number: 11263175
    Abstract: An apparatus includes a processor to: within each reading thread, retrieve a data set part and corresponding part metadata from storage device(s), analyze row group metadata for each row group within the data set part to identify candidate row group(s) meeting specified criteria, and store the candidate row group(s) and corresponding row group metadata within a data buffer of a queue; operate the queue as a FIFO buffer; within each provision thread, retrieve one of multiple row groups and corresponding metadata from within the data buffer, use information in the metadata to identify rows meeting the criteria, and provide those rows to the requesting device or an application; and in response to each instance of storage of a data set part within a data buffer of the queue, analyze the availability of storage space and/or of processing resources to determine whether to dynamically adjust the quantity of reading threads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 1, 2022
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener, Richard Todd Knight
  • Patent number: 10990564
    Abstract: An apparatus includes a processor to: within each collection thread, assemble a row group from stored rows, generate row group metadata corresponding to the row group, and store the row group and row group metadata within a data buffer of a queue; operate the queue as a FIFO buffer; within each aggregation thread, retrieve multiple row groups and corresponding row group metadata from multiple data buffers of the queue, assemble a data set part from the multiple row groups, generate part metadata that includes the row group metadata, and transmit, to storage device(s) and/or a requesting device, the data set part and/or the part metadata; and in response to each retrieval of at least a row group from a data buffer of the queue for an aggregation thread, analyze availability of storage space within the node device to determine whether to dynamically adjust the quantity of data buffers.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 27, 2021
    Assignee: SAS INSTITUTE INC.
    Inventor: Brian Payton Bowman
  • Patent number: 10983957
    Abstract: An apparatus includes a processor to: instantiate collection threads, data buffers of a queue, and aggregation threads; within each collection thread, assemble a row group from a subset of the multiple rows, reorganize the data values row-wise to columnar organization, and store the row group within a data buffer of the queue; operate the buffer queue as a FIFO buffer; within each aggregation thread, retrieve multiple row groups from multiple data buffers of the queue, assemble a data set part from the multiple row groups, transmit, to storage device(s) via a network, the data set part; and in response to each instance of retrieval of a row group from a data buffer of the buffer queue for use within an aggregation thread, analyze a level of availability of at least storage space within the node device to determine whether to dynamically adjust the quantity of data buffers of the buffer queue.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 20, 2021
    Assignee: SAS INSTITUTE INC.
    Inventor: Brian Payton Bowman
  • Publication number: 20210042265
    Abstract: An apparatus includes a processor to: instantiate collection threads, data buffers of a queue, and aggregation threads; within each collection thread, assemble a row group from a subset of the multiple rows, reorganize the data values row-wise to columnar organization, and store the row group within a data buffer of the queue; operate the buffer queue as a FIFO buffer; within each aggregation thread, retrieve multiple row groups from multiple data buffers of the queue, assemble a data set part from the multiple row groups, transmit, to storage device(s) via a network, the data set part; and in response to each instance of retrieval of a row group from a data buffer of the buffer queue for use within an aggregation thread, analyze a level of availability of at least storage space within the node device to determine whether to dynamically adjust the quantity of data buffers of the buffer queue.
    Type: Application
    Filed: September 29, 2020
    Publication date: February 11, 2021
    Applicant: SAS Institute Inc.
    Inventor: Brian Payton Bowman
  • Publication number: 20210026805
    Abstract: An apparatus includes a processor to: instantiate data buffers of a queue, reading threads, and provision threads; within each reading thread, use an identifier provided in a data buffer of the queue to retrieve the corresponding data set part and part metadata from storage device(s), and store both within the data buffer; operate the queue as a (FIFO) buffer; within each provision thread, retrieve a row group from among multiple row groups and corresponding metadata from within the data buffer, use information in the metadata to decompress at least one column, and provide the data values of the row group to the requesting device or an application routine; and in response to each instance of storage of a data set part within a data buffer of the queue, analyze the availability of storage space and/or of processing resources to determine whether to dynamically adjust the quantity of reading threads.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener
  • Publication number: 20210026806
    Abstract: An apparatus includes a processor to: within each reading thread, retrieve a data set part and corresponding part metadata from storage device(s), analyze row group metadata for each row group within the data set part to identify candidate row group(s) meeting specified criteria, and store the candidate row group(s) and corresponding row group metadata within a data buffer of a queue; operate the queue as a FIFO buffer; within each provision thread, retrieve one of multiple row groups and corresponding metadata from within the data buffer, use information in the metadata to identify rows meeting the criteria, and provide those rows to the requesting device or an application; and in response to each instance of storage of a data set part within a data buffer of the queue, analyze the availability of storage space and/or of processing resources to determine whether to dynamically adjust the quantity of reading threads.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener, Richard Todd Knight
  • Publication number: 20210019284
    Abstract: An apparatus includes a processor to: within each collection thread, assemble a row group from stored rows, generate row group metadata corresponding to the row group, and store the row group and row group metadata within a data buffer of a queue; operate the queue as a FIFO buffer; within each aggregation thread, retrieve multiple row groups and corresponding row group metadata from multiple data buffers of the queue, assemble a data set part from the multiple row groups, generate part metadata that includes the row group metadata, and transmit, to storage device(s) and/or a requesting device, the data set part and/or the part metadata; and in response to each retrieval of at least a row group from a data buffer of the queue for an aggregation thread, analyze availability of storage space within the node device to determine whether to dynamically adjust the quantity of data buffers.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Applicant: SAS Institute Inc.
    Inventor: Brian Payton Bowman
  • Patent number: 10789207
    Abstract: An apparatus includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong; following block exchanges redistributing the subsets among a reduced number of node devices, receive sizes of blocks or sub-blocks of data within each subset from the reduced number of node devices; based on the received sizes, generate map data organized to define an ordering among the blocks stemming from the ordering among the multiple node devices; determine whether the total size of the map data and metadata, together, exceeds a minimum size for data transmissions to storage device(s); and in response to the total size exceeding the minimum size, form the map data and metadata into segment(s) that each fit the minimum size and a maximum size, and transmit the segment(s) at least partially in parallel with other segments of the blocks transmitted by the reduced number of node devices.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 29, 2020
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Patent number: 10402372
    Abstract: An apparatus includes a processor component to receive a node device identifier defining an ordering among multiple node devices and among multiple blocks of data distributed among the multiple node devices, and transmit a size of a first subset of the multiple blocks stored within the node device to a control device. In response to receiving instructions to receive a second subset from another node device, perform operations including: receive and store the second subset; group the blocks of data of the first and second subsets into multiple segments in an order that corresponds to the ordering among the multiple blocks, wherein each segment is sized to fit minimum and maximum sizes for transmission to storage device(s); transmit the multiple segments to the storage device(s); and relay multiple segment identifiers from the storage device(s) to the control device in an order corresponding to the ordering among the multiple segments.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 3, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Publication number: 20190197021
    Abstract: An apparatus of includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong and among subsets of multiple blocks of data distributed thereamong; receive sizes of the subsets from the multiple node devices; derive block exchanges among the multiple node device based on the sizes and a minimum size imposed on data transmissions to storage device(s); and transmit a block exchange vector that describes the block exchanges to the multiple node devices, wherein: the subsets remain distributed among a reduced number of the multiple node devices following the block exchanges; at least all node devices of the reduced number but one stores an amount of the blocks of data exceeding the minimum size; and the block exchanges are all lower-order to higher-order node device transfers, or all higher-order to lower-order node device transfers.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 27, 2019
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Patent number: 10311023
    Abstract: An apparatus of includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong and among subsets of multiple blocks of data distributed thereamong; receive sizes of the subsets from the multiple node devices; derive block exchanges among the multiple node device based on the sizes and a minimum size imposed on data transmissions to storage device(s); and transmit a block exchange vector that describes the block exchanges to the multiple node devices, wherein: the subsets remain distributed among a reduced number of the multiple node devices following the block exchanges; at least all node devices of the reduced number but one stores an amount of the blocks of data exceeding the minimum size; and the block exchanges are all lower-order to higher-order node device transfers, or all higher-order to lower-order node device transfers.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 4, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Patent number: 10303670
    Abstract: An apparatus including a processor to index data records within a data cell, wherein for each data record, the processor retrieves data values from first and second data fields; determines whether the first and second data fields store unique data values; in response to the first data field storing a unique data value, adds an identifier of the data record to a first unique values index, in response to the second data field storing a unique data value, adds the identifier to a second unique values index, wherein identifiers of data records within the unique values indexes are ordered based on corresponding unique data values; and generates an indication of ranges of data values of the first and second data fields to enable a determination of whether a data value specified in search criteria is present within at least the data cell.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: May 28, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener, Steven E. Krueger
  • Publication number: 20190129887
    Abstract: An apparatus includes a processor component to receive a node device identifier defining an ordering among multiple node devices and among multiple blocks of data distributed among the multiple node devices, and transmit a size of a first subset of the multiple blocks stored within the node device to a control device. In response to receiving instructions to receive a second subset from another node device, perform operations including: receive and store the second subset; group the blocks of data of the first and second subsets into multiple segments in an order that corresponds to the ordering among the multiple blocks, wherein each segment is sized to fit minimum and maximum sizes for transmission to storage device(s); transmit the multiple segments to the storage device(s); and relay multiple segment identifiers from the storage device(s) to the control device in an order corresponding to the ordering among the multiple segments.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Publication number: 20190129888
    Abstract: An apparatus includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong; following block exchanges redistributing the subsets among a reduced number of node devices, receive sizes of blocks or sub-blocks of data within each subset from the reduced number of node devices; based on the received sizes, generate map data organized to define an ordering among the blocks stemming from the ordering among the multiple node devices; determine whether the total size of the map data and metadata, together, exceeds a minimum size for data transmissions to storage device(s); and in response to the total size exceeding the minimum size, form the map data and metadata into segment(s) that each fit the minimum size and a maximum size, and transmit the segment(s) at least partially in parallel with other segments of the blocks transmitted by the reduced number of node devices.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Jeff Ira Cleveland, III
  • Patent number: 10185722
    Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 22, 2019
    Assignee: SAS INSTITUTE INC.
    Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
  • Patent number: 10185721
    Abstract: An apparatus includes a processor component caused to: retrieve metadata of organization of data within a data set, and map data of organization of data blocks within a data file; receive indications of which node devices are available to perform a processing task with a data set portion; and in response to the data set including partitioned data, compare the quantities of available node devices and of the node devices last involved in storing the data set. In response to a match, for each map data map entry: retrieve a hashed identifier for a data sub-block, and a size for each of the data sub-blocks within the corresponding data block; divide the hashed identifier by the quantity of available node devices; compare the modulo value to a designation assigned to each of the available node devices; and provide a pointer to the available node device assigned the matching designation.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 22, 2019
    Assignee: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Steven E. Krueger, Richard Todd Knight, Chih-Wei Ho
  • Publication number: 20180276259
    Abstract: An apparatus including a processor to index data records within a data cell, wherein for each data record, the processor retrieves data values from first and second data fields; determines whether the first and second data fields store unique data values; in response to the first data field storing a unique data value, adds an identifier of the data record to a first unique values index, in response to the second data field storing a unique data value, adds the identifier to a second unique values index, wherein identifiers of data records within the unique values indexes are ordered based on corresponding unique data values; and generates an indication of ranges of data values of the first and second data fields to enable a determination of whether a data value specified in search criteria is present within at least the data cell.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener, Steven E. Krueger
  • Publication number: 20180276231
    Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicant: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
  • Patent number: 10013441
    Abstract: An apparatus including a processor to: index multiple data records within a data cell by first and second data fields in a single read pass through the data cell; wherein for each data record within the first data cell, the processor is to retrieve data values from the first and second data fields, search a first binary tree to determine whether the data value from the first data field comprises a unique value, and add the data value to the first binary tree if it is unique, and search a second binary tree to determine whether the data value from the second data field comprises a unique value, and add the data value to the second binary tree if it is unique; and generate a first and second unique values indexes of identifiers of the data records associated with the unique data values within the first and second binary trees.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 3, 2018
    Assignee: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Gordon Lyle Keener, Steven E. Krueger