Patents by Inventor Brian Piccione

Brian Piccione has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961870
    Abstract: Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 16, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Brian Piccione, Mark Itzler, Xudong Jiang, Krystyna Slomkowski, Harold Y. Hwang, John L. Hostetler
  • Publication number: 20240120350
    Abstract: An image sensing device including a Geiger-mode avalanche photodiode (GmAPD), a read out integrated circuit (ROIC), and a limit resistor connected to the GmAPD and the ROIC in series, wherein the ROIC includes an active quenching circuit.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Mark Allen ITZLER, Brian PICCIONE, Xudong JIANG, Krystyna SLOMKOWSKI
  • Publication number: 20240037768
    Abstract: A computer-based system may quantify, based on the plurality of instances of a feature indicated by image data, an attribute (e.g., a color, a shape, a material, a texture, etc.) of the plurality of instances of the feature. The system may also quantify an attribute of an instance of the feature of the plurality of instances of the feature. The system may modify the image data to indicate the instance of the feature if/when a value of the quantified attribute of the instance of the feature exceeds a value of the quantified attribute of the plurality of instances of the feature by a threshold. Functionality (e.g., defective, non-defective, potentially defective, etc.) of the unit may be classified based on the modified image data.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 1, 2024
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Frederick Seng, Harold HWANG, Brian PICCIONE, Kuen-Ting SHIU
  • Patent number: 11888000
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 30, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Mark Allen Itzler, Brian Piccione, Xudong Jiang, Krystyna Slomkowski
  • Publication number: 20220165782
    Abstract: Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Applicant: ARGO AI, LLC
    Inventors: Brian PICCIONE, Mark ITZLER, Xudong JIANG, Krystyna SLOMKOWSKI, Harold Y. HWANG, John L. HOSTETLER
  • Publication number: 20220149086
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: ARGO AI, LLC
    Inventors: Mark Allen ITZLER, Brian PICCIONE, Xudong JIANG, Krystyna SLOMKOWSKI
  • Patent number: 11289532
    Abstract: Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 29, 2022
    Assignee: Argo Al, LLC
    Inventors: Brian Piccione, Mark Itzler, Xudong Jiang, Krystyna Slomkowski, Harold Y. Hwang, John L. Hostetler
  • Publication number: 20220077222
    Abstract: Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Applicant: Argo AI, LLC
    Inventors: Brian Piccione, Mark Itzler, Xudong Jiang, Krystyna Slomkowski, Harold Y. Hwang, John L. Hostetler
  • Patent number: 11233076
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 25, 2022
    Assignee: ARGO AI, LLC
    Inventors: Mark Allen Itzler, Brian Piccione, Xudong Jiang, Krystyna Slomkowski
  • Publication number: 20210408089
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Mark Allen ITZLER, Brian PICCIONE, Xudong JIANG, Krystyna SLOMKOWSKI
  • Patent number: 10367111
    Abstract: An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed partially through the backside (substrate) of each APD in the array, wherein the via is offset from the active region of each said APD.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 30, 2019
    Assignee: ARGO AI, LLC
    Inventors: Brian Piccione, Mark Allen Itzler
  • Publication number: 20180358391
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 13, 2018
    Inventors: Mark Allen ITZLER, Brian PICCIONE, Xudong JIANG, Krystyna SLOMKOWSKI
  • Patent number: 10134936
    Abstract: An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed through the backside (substrate) of each APD in the array.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 20, 2018
    Assignee: ARGO AI, LLC
    Inventors: Brian Piccione, Mark Allen Itzler
  • Publication number: 20180198016
    Abstract: An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed partially through the backside (substrate) of each APD in the array, wherein the via is offset from the active region of each said APD.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Inventors: Brian Piccione, Mark Allen Itzler
  • Patent number: 9935138
    Abstract: A scalable fuse design for individual pixels of a focal plane array of photodiodes comprises a fuse disposed on the upper surface of each photodiode in the array, wherein the fuse is situated proximal to a side of each photodiode. The fuse of each photodiode is electrically coupled to the active region thereof via a first bus and is electrically coupled to an ROIC via a second bus.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 3, 2018
    Assignee: Argo AI, LLC
    Inventors: Brian Piccione, Xudong Jiang, Krys Slomkowski, Mark Allen Itzler
  • Publication number: 20170250209
    Abstract: A scalable fuse design for individual pixels of a focal plane array of photodiodes comprises a fuse disposed on the upper surface of each photodiode in the array, wherein the fuse is situated proximal to a side of each photodiode. The fuse of each photodiode is electrically coupled to the active region thereof via a first bus and is electrically coupled to an ROIC via a second bus.
    Type: Application
    Filed: December 27, 2016
    Publication date: August 31, 2017
    Inventors: Brian Piccione, Xudong Jiang, Krys Slomkowski, Mark Allen Itzler
  • Publication number: 20170084773
    Abstract: An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed through the backside (substrate) of each APD in the array.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 23, 2017
    Inventors: Brian Piccione, Mark Allen Itzler