Patents by Inventor Brian R. Butcher

Brian R. Butcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11045250
    Abstract: A surgical instrument includes a housing, an energizable member, a powered deployment assembly, and a cable assembly. The energizable member is configured to supply electrosurgical energy to tissue, and is movable between a storage position and a deployed position. The powered deployment assembly is configured to selectively move the energizable member between the storage position and the deployed position. The cable assembly having a cable coupled to the housing at a first end and having a plug coupled to the cable at a second, opposite end. The cable housing one or more first wires for selectively providing electrosurgical energy to the energizable member and one or more second wires for selectively providing power to the powered deployment assembly. The plug is configured to house a battery therein for powering the powered deployment assembly via the one or more second wires.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 29, 2021
    Assignee: Covidien LP
    Inventors: Daniel A. Joseph, Brian R. Butcher, Amarsinh D. Jadhav, Purvish Soni
  • Patent number: 10103088
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel IP Corporation
    Inventors: Quan Qi, Brian R. Butcher, Carlton E. Hanna, Hong Wei Hu
  • Publication number: 20180286780
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Intel IP Corporation
    Inventors: Quan Qi, Brian R. Butcher, Carlton E. Hanna, Hong Wei Hu
  • Publication number: 20180103997
    Abstract: A surgical instrument includes a housing, an energizable member, a powered deployment assembly, and a cable assembly. The energizable member is configured to supply electrosurgical energy to tissue, and is movable between a storage position and a deployed position. The powered deployment assembly is configured to selectively move the energizable member between the storage position and the deployed position. The cable assembly having a cable coupled to the housing at a first end and having a plug coupled to the cable at a second, opposite end. The cable housing one or more first wires for selectively providing electrosurgical energy to the energizable member and one or more second wires for selectively providing power to the powered deployment assembly. The plug is configured to house a battery therein for powering the powered deployment assembly via the one or more second wires.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 19, 2018
    Inventors: DANIEL A. JOSEPH, BRIAN R. BUTCHER, AMARSINH D. JADHAV, PURVISH SONI
  • Patent number: 9867656
    Abstract: A surgical instrument includes a housing, an energizable member, a powered deployment assembly, and a cable assembly. The energizable member is configured to supply electrosurgical energy to tissue, and is movable between a storage position and a deployed position. The powered deployment assembly is configured to selectively move the energizable member between the storage position and the deployed position. The cable assembly having a cable coupled to the housing at a first end and having a plug coupled to the cable at a second, opposite end. The cable housing one or more first wires for selectively providing electrosurgical energy to the energizable member and one or more second wires for selectively providing power to the powered deployment assembly. The plug is configured to house a battery therein for powering the powered deployment assembly via the one or more second wires.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: January 16, 2018
    Assignee: COVIDIEN LP
    Inventors: Daniel A. Joseph, Brian R. Butcher, Amarsinh D. Jadhav, Purvish Soni
  • Publication number: 20160135868
    Abstract: A surgical instrument includes a housing, an energizable member, a powered deployment assembly, and a cable assembly. The energizable member is configured to supply electrosurgical energy to tissue, and is movable between a storage position and a deployed position. The powered deployment assembly is configured to selectively move the energizable member between the storage position and the deployed position. The cable assembly having a cable coupled to the housing at a first end and having a plug coupled to the cable at a second, opposite end. The cable housing one or more first wires for selectively providing electrosurgical energy to the energizable member and one or more second wires for selectively providing power to the powered deployment assembly. The plug is configured to house a battery therein for powering the powered deployment assembly via the one or more second wires.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 19, 2016
    Inventors: DANIEL A. JOSEPH, BRIAN R. BUTCHER, AMARSINH D. JADHAV, PURVISH SONI
  • Patent number: 8236578
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: August 7, 2012
    Assignee: Everspin Technologies, Inc.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • Publication number: 20120122247
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • Patent number: 8119424
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 21, 2012
    Assignee: Everspin Technologies, Inc.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • Patent number: 7833806
    Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: November 16, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Kenneth H. Smith, Nicholas D. Rizzo, Sanjeev Aggarwal, Anthony Ciancio, Brian R. Butcher, Kelly Wayne Kyler
  • Publication number: 20100197043
    Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Nicholas D. RIZZO, Kenneth H. SMITH, Sanjeev AGGARWAL, Anthony CIANCIO, Brian R. BUTCHER, Kelly Wayne KYLER
  • Patent number: 7602177
    Abstract: An apparatus (46, 416, 470) is provided for sensing physical parameters. The apparatus (46, 416, 470) comprises a magnetic tunnel junction (MTJ) (32, 432), first and second electrodes (36, 38, 426, 434), a magnetic field source (MFS) (34, 445, 476) whose magnetic field (35) overlaps the MTJ (32, 432) and a moveable magnetic cladding element (33, 448, 478) whose proximity (43, 462, 479, 479?) to the MFS (34, 445, 476) varies in response to an input to the sensor. The MFS (34, 445, 476) is located between the cladding element (33, 448, 478) and the MTJ (32, 432). Motion (41, 41?, 41-1, 464, 477) of the cladding element (33, 448, 478) relative to the MFS (34, 445, 476) in response to sensor input causes the magnetic field (35) at the MTJ (32, 432) to change, thereby changing the electrical properties of the MTJ (32, 432). A one-to-one correspondence (54) between the sensor input and the electrical properties of the MTJ (32, 432) is obtained.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: October 13, 2009
    Assignee: Everspin Technologies, Inc.
    Inventors: Brian R. Butcher, Kenneth H. Smith, Bradley N. Engel
  • Publication number: 20090085058
    Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Phillip G. Mather, Sanjeev Aggarwal, Brian R. Butcher, Renu W. Dave, Frederick B. Mancoff, Nicholas D. Rizzo
  • Patent number: 7494825
    Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian R. Butcher, Kerry J. Nagel, Kenneth H. Smith
  • Patent number: 7476329
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 13, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Patent number: 7445943
    Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: November 4, 2008
    Assignee: Everspin Technologies, Inc.
    Inventors: Kenneth H. Smith, Brian R. Butcher, Gregory W. Grynkewich, Srinivas V. Pietambaram, Nicholas D. Rizzo
  • Publication number: 20080160640
    Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Inventors: Brian R. Butcher, Kerry J. Nagel, Kenneth H. Smith
  • Publication number: 20080096290
    Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Kenneth H. Smith, Brian R. Butcher, Gregory W. Grynkewich, Srinivas V. Pietambaram, Nicholas D. Rizzo
  • Patent number: 7279341
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam
  • Patent number: 7169622
    Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: January 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Clarence J. Tracy