Patents by Inventor Brian R. Kessler

Brian R. Kessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing logic and embedded memory in parallel
    Patent number: 7103814
    Abstract: Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: William R. Corbin, Brian R. Kessler, Erik A. Nelson, Thomas E. Obremski, Donald L. Wheater
  • Testing logic and embedded memory in parallel
    Publication number: 20040083412
    Abstract: Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Applicant: International Business Machines Corporation
    Inventors: William R. Corbin, Brian R. Kessler, Erik A. Nelson, Thomas E. Obremski, Donald L. Wheater