Abstract: In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

Abstract: In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

Abstract: Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.

Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.

Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: Systems and methods for sorting a data set stored on an external device. A plurality of smaller radix sizes are determined, based on a first radix size and performance characteristics of an external data storage device, whose sizes add up to a first radix size for an in-place radix sort. The smaller radix sizes reduce a total time to perform the in-place radix sort. Each level of a multiple level in-place radix sort is performed with the smaller radix sizes. Each level of the sort includes dividing the data set into N buckets; dividing the buffer into N buckets; and iteratively loading a respective segment in each bucket of the data set into a respective bucket of the buffer, performing an in-place radix sort on the data in the buffer, and returning sorted buffer data to the data set on the external storage device.

Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.

Abstract: A low level virtual machine (LLVM)-based system C compiler for architecture synthesis is provided. In one aspect, a method for translating a system C model to hardware description language (HDL) is provided. The method includes the steps of: generating a hardware connection model (HCM) from the system C model, wherein the HCM defines modules and interconnects in a hardware system; parsing the system C model into a LLVM intermediate representation (IR); converting the LLVM IR to a system LLVM IR which records correspondence information between the LLVM IR and the HCM; and generating the HDL based on direct mapping of processes from the system LLVM IR and the HCM.

Abstract: A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content addressable memory elements and a plurality of columns of content addressable memory elements is provided. Each of the content addressable memory elements further includes a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID), where an input bit to each of the content addressable memory elements is compared with: (1) a first state of the first SQUID and (2) a second state of the second SQUID to generate an output signal. The memory system further includes a Josephson magnetic random access memory (JMRAM), coupled to the content addressable memory.

Abstract: A technique for mapping logical threads to physical threads of a simultaneous multithreading (SMT) data processing system includes mapping one or more logical threads to one or more physical threads based on a selected SMT mode for a processor. In this case, respective resources for each of the one or more physical threads are predefined based on the SMT mode and an identifier of the one or more physical threads. The one or more physical threads are then executed on the processor utilizing the respective resources.

Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.

Abstract: A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content addressable memory elements and a plurality of columns of content addressable memory elements is provided. Each of the content addressable memory elements further includes a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID), where an input bit to each of the content addressable memory elements is compared with: (1) a first state of the first SQUID and (2) a second state of the second SQUID to generate an output signal. The memory system further includes a Josephson magnetic random access memory (JMRAM), coupled to the content addressable memory.

Abstract: Systems and methods for sorting a data set stored on an external device. A plurality of smaller radix sizes are determined, based on a first radix size and performance characteristics of an external data storage device, whose sizes add up to a first radix size for an in-place radix sort. The smaller radix sizes reduce a total time to perform the in-place radix sort. Each level of a multiple level in-place radix sort is performed with the smaller radix sizes. Each level of the sort includes dividing the data set into N buckets; dividing the buffer into N buckets; and iteratively loading a respective segment in each bucket of the data set into a respective bucket of the buffer, performing an in-place radix sort on the data in the buffer, and returning sorted buffer data to the data set on the external storage device.

Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.

Abstract: Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history. In another aspect, the global history vector may be implemented with a circular buffer structure. Youngest and oldest pointers to the circular buffer are maintained and used in recovery.

Abstract: In a computing system running an environment for designing operation of circuitry, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including access to the pipeline, wherein the pipeline access allows the one or more user-defined modules to interact indirectly. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.

Abstract: In a computing system running an environment for designing operation of circuity, at least the following are performed for providing simulations and evaluations of one or more user-defined modules of circuitry including one or more pipeline stages in a pipeline. A model of the pipeline is automatically generated by using a pipeline block diagram, where the model is generated in a high-level modeling language able to perform simulations of circuitry with the pipeline. An interface is automatically generated between the one or more user-defined modules and the generated model of the pipeline, the interface including a set of access methods to the pipeline. Evaluation is performed of the one or more user-defined modules using the automatically generated model of the pipeline and the automatically generated interface. Methods, apparatus, and computer program products are disclosed.