Abstract: A Layered Network system may provide varying cost from order NlogN low-cost networds, to completely-routing, fully-Layered networks with cots of order Nlog .sup.3 N. Layered networks are composed of switches and point-to-point connections between them. These networks establish connections from requestors to responders by relaying "requests" through the switches. Each switch has built-in control logic to route requests and responses. The switch setting is determined using the comparison of the request with the request's current location in the network, and with locally competing requests. To provide distributed routing without a centralized controller, each switch routes the requests using only the information contained in the requests that switch handles. The switch setting is remembered in order to route the responses on the same paths as the associated requests, but in the reverse direction.

Abstract: A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0".

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N.