Abstract: A method and apparatus for processing a digital signal by a fast Fourier transformation using balanced coefficients. The balanced coefficient method reduces the number of coefficients required to process an FFT of size 2.sup.p from a total of 2.sup.p coefficients to p times the square root of 2.sup.p. The new system employs a reduced number of coefficients in a unique addressing scheme to produce a cheaper, lighter, smaller, cooler FFT processor which uses less power and is more reliable.

Abstract: A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders, to allow slower bits to skip past a stage while faster bits must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.

Abstract: Level sensitive scan design (LSSD) scan strings on an integrated digital logic circuit chip are employed for multiple functions of providing control parameters to logic blocks on the integrated circuit chip, and for providing reconfiguration messages to reconfiguration logic on the integrated circuit chip, in addition to the normal function of transferring test data to various portions of the integrated circuit chip. This reduces the number of input/output pads on the integrated circuit chip which must be dedicated to these functions.