Abstract: A rate-adaptive pacemaker and a method for its operation in which the response factor for a minute ventilation sensor or other type of exertion level sensor is automatically set during a parameter adjustment mode that utilizes an activity level measurement to determine when the patient is at a target activity level with which is associated an appropriate target pacing rate. In a preferred embodiment, the target activity level corresponds to casual walking (e.g., 2 mph at a 4% grade) with a target pacing rate selected as appropriate for that level of activity in the individual patient.

Abstract: A rate-adaptive pacemaker and a method for its operation in which the response factor for a minute ventilation sensor or other type of exertion level sensor is automatically set during a parameter adjustment mode that utilizes an activity level measurement to determine when the patient is at a target activity level with which is associated an appropriate target pacing rate. In a preferred embodiment, the target activity level corresponds to casual walking (e.g., 2 mph at a 4% grade) with a target pacing rate selected as appropriate for that level of activity in the individual patient.

Abstract: Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred “layered network” of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.

Abstract: Dense physical and electrical connection of (i) flat flexible multiconductor cables of the printed circuit or ribbon types, to (ii) to spaced-parallel planar modules, particularly to switching modules containing switching chips, is realized by (1) a particular connection geometry in combination with (2) a spring clip connector. Flat flexible multiconductor cables routed through free space either in (i) “X” and, optionally also, “Z” planes, or else in (ii) “Y” planes exclusively, have their conductors' ends stripped and bent 90° so as to lie upon conductive pads, arrayed along lines angled 45° to both the “X” and “Y” planes, located on the substrates of switching modules that are within “Z” planes.

Abstract: Multi-stage switching networks may be constructed and expanded from small to very large networks that are contained within a compact physical volume. This is accomplished by replication of a pre-selected network module containing switches by a rotating, folding and squaring process that substantially reduces the length of connections between switches. This geometry allows very large networks by inductively combining smaller networks into larger networks. In networks constructed with this geometry, the length of the longest connections between switches is proportional to the square root of the number of ports provided by the network.

Abstract: An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Abstract: This invention computes by constructing a lattice of states. Every lattice of states corresponding to correct execution satisfies the temporal logic formula comprising a Definitive Axiomatic Notation for Concurrent Execution (DANCE) program. This invention integrates into a state-lattice computational model: a polymorphic, strong type system; visibility-limiting domains; first-order assertions; and logic for proving a program correctness. This invention includes special hardware means for elimination of cache coherency among other things, necessary to construct state-lattices concurrently. The model of computation for the DANCE language consisting of four, interrelated, logical systems describing state-lattices, types, domains, and assertions. A fifth logical system interrelates the other four systems allowing proofs of program correctness. The method of the present invention teaches programs as temporal formulas satisfied by lattices of states corresponding to correct execution.