Abstract: An approach is provided for determining an optimal path for searching a branch target buffer (BTB). Initial BTB search index results are generated by searching a prediction latency-optimized first accelerator. The initial BTB search index results are added as tentative items in a search index list. Other BTB search index results are generated by searching a capacity-optimized second accelerator. The first and second accelerators run concurrently. Difference(s) are determined between one or more results of the other BTB search index results and one or more results of the initial BTB search index results based on a comparison between respective results in the other BTB search index results and the initial BTB search index results. The one or more results of the initial BTB search index results are replaced in the search index list with the one or more results of the other BTB search index results.

Abstract: An approach is provided for determining an optimal path for searching a branch target buffer (BTB). Initial BTB search index results are generated by searching a prediction latency-optimized first accelerator. The initial BTB search index results are added as tentative items in a search index list. Other BTB search index results are generated by searching a capacity-optimized second accelerator. The first and second accelerators run concurrently. Difference(s) are determined between one or more results of the other BTB search index results and one or more results of the initial BTB search index results based on a comparison between respective results in the other BTB search index results and the initial BTB search index results. The one or more results of the initial BTB search index results are replaced in the search index list with the one or more results of the other BTB search index results.

Abstract: A branch prediction logic system includes a branch history table (BHT), a multi-level history table, and a prediction update queue. The BHT includes a plurality of lines, each line corresponding to at least one branch instruction and containing history information specific to the at least one branch instruction. A first pattern history table (PHT-1) stores first branch data corresponding to the at least one branch instruction included in a given line of the BHT and a second pattern history table (PHT-2) stores second branch data corresponding to the at least one branch instruction included in a given line. The prediction update queue stores a line presence bit having one of a “1” logic state or a “0” logic state. The branch prediction logic system performs a data swap between the PHT-2 and the PHT-1 based on the logic state of the line presence bit.

Abstract: A branch prediction unit of the processor powers-up and accesses only a subset of a plurality of prediction structures to obtain a first set of branch prediction information for a conditional branch. During the access, at least one of the plurality of prediction structures remains powered-down. The branch prediction unit thereafter determines whether all of the plurality of prediction structures having branch prediction information relevant to the conditional branch were accessed. Based on a determination that fewer than all of the plurality of prediction structures having branch prediction information relevant to the conditional branch were accessed, the branch prediction unit refrains from outputting a branch prediction based on the first set of branch prediction information, powers-up and accesses a greater number of the plurality of prediction structures to obtain a second set of branch prediction information, and outputs a branch prediction based on the second set of branch prediction information.

Abstract: A branch prediction logic system includes a branch history table (BHT), a multi-level history table, and a prediction update queue. The BHT includes a plurality of lines, each line corresponding to at least one branch instruction and containing history information specific to the at least one branch instruction. A first pattern history table (PHT-1) stores first branch data corresponding to the at least one branch instruction included in a given line of the BHT and a second pattern history table (PHT-2) stores second branch data corresponding to the at least one branch instruction included in a given line. The prediction update queue stores a line presence bit having one of a “1” logic state or a “0” logic state. The branch prediction logic system performs a data swap between the PHT-2 and the PHT-1 based on the logic state of the line presence bit.

Abstract: A method of branch prediction in a processor includes: generating a new line index and an intraline index; generating a first output of a pattern-based predictor structure using the new line index; generating a second output of the pattern-based predictor structure using the intraline index; selecting one of the first output and the second output based on a result of a prediction pipeline; and predicting a direction of a branch using the selected one of the first output and the second output.

Abstract: A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

Abstract: A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Abstract: Embodiments include a hierarchical metadata prediction system that includes a first line-based predictor having a first line for storage of metadata entries, and a second line-based predictor configured to store metadata entries from the first line-based predictor. The second line-based predictor has a second line, the second line including a plurality of containers, the plurality of containers including at least a first set of containers having a first size and a second set of containers having a second size. The system also includes a processing device configured to transfer one or more metadata entries between the first line-based predictor and the second-line based predictor. Embodiments also include a computer-implemented method and a computer program product.

Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Abstract: Aspects of the invention include a computer-implemented method of updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions will resolve and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions resolved in one of a plurality of prescribed manners relative to the prediction and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions resolved in one of the plurality of prescribed manners.

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.

Abstract: Embodiments are provided for using metadata presence information to determine when to access a higher-level metadata table. It is determined that an incomplete hit occurred for a line of metadata in a lower-level structure of a processor, the lower-level structure being coupled to a higher-level structure in a hierarchy. It is determined that metadata presence information in a metadata presence table is a match to the line of metadata from the lower-level structure. Responsive to determining the match, it is determined to avoid accessing the higher-level structure of the processor.

Abstract: A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Abstract: A method of branch prediction in a processor includes: obtaining, by the processor, a branch instruction for which a direction of a branch is to be predicted; generating, by the processor, an index based on an instruction address, a global path vector (GPV), and a counter; selecting, by the processor, an entry from a data structure using the index; and predicting, by the processor, the direction of the branch using information included in the selected entry. The method may include modifying a tag in the selected entry based at least in part on another GPV.

Abstract: A cache compression predictor can be coupled to a central processing unit (CPU) CPU core. The CPU core can read a cache line from a cache. Upon the CPU core reading the cache line, the cache compression predictor can predict whether the cache line is a compressed cache line or an uncompressed cache line.

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Abstract: Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.

Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.