Patents by Inventor Brian Robert Wiese

Brian Robert Wiese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9306733
    Abstract: A method of synchronizing a time division duplex (TDD) multi-line, multi-carrier data communication system is provided. Synchronization is established using unique pseudo-random bit sequences (PRBS) from a common generator polynomial having different seed values. Due to low correlation of PRBS generated with different seed values, a remote unit can only synchronize to its intended signal effectively mitigating far-end and near-end crosstalk impact of large bandwidth very high speed digital subscriber lines (VDSL).
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 5, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Kevin Zhifang Du, Brian Robert Wiese, Michael Eugene Locke, Richard Glentworth Greenfield
  • Publication number: 20140241384
    Abstract: A method of synchronizing a time division duplex (TDD) multi-line, multi-carrier data communication system is provided. Synchronization is established using unique pseudo-random bit sequences (PRBS) from a common generator polynomial having different seed values. Due to low correlation of PRBS generated with different seed values, a remote unit can only synchronize to its intended signal effectively mitigating far-end and near-end crosstalk impact of large bandwidth very high speed digital subscriber lines (VDSL).
    Type: Application
    Filed: November 27, 2013
    Publication date: August 28, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Kevin Zhifang Du, Brian Robert Wiese, Michael Eugene Locke, Richard Glentworth Greenfield
  • Patent number: 6993099
    Abstract: A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: January 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Nicholas Zogakis, Michael Locke, Brian Robert Wiese
  • Publication number: 20030086509
    Abstract: A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.
    Type: Application
    Filed: November 7, 2001
    Publication date: May 8, 2003
    Inventors: Thomas Nicholas Zogakis, Michael Locke, Brian Robert Wiese