Patents by Inventor Brian Romanczyk
Brian Romanczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12660228Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.Type: GrantFiled: June 21, 2021Date of Patent: June 16, 2026Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Brian Romanczyk, Umesh K. Mishra, Pawana Shrestha, Matthew Guidry, James Buckwalter, Stacia Keller, Rohit Reddy Karnaty
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Publication number: 20260013170Abstract: N-polar HEMT structures and methods of forming HEMT structures. An example semiconductor device includes a III-N material structure, comprising: a III-N backbarrier layer; a III-N channel layer over an N-face of the III-N backbarrier layer; and an n+ III-N etch stop layer over an N-face of the III-N channel layer. The semiconductor device includes: a gate region between a source region and a drain region; a source contact over the n+ III-Netch stop layer in the source region; a drain contact over the n+ III-N etch stop layer in the drain region; a 2DEG in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N backbarrier layer; a channel recess etched through the n+ III-N etch stop layer between the source region and the drain region; and a gate recess in the channel layer and a gate contact in the gate recess.Type: ApplicationFiled: October 17, 2023Publication date: January 8, 2026Inventors: Brian ROMANCZYK, Matthew GUIDRY, Pawana SHRESTHA
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Publication number: 20250125265Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.Type: ApplicationFiled: December 20, 2024Publication date: April 17, 2025Inventors: Brian ROMANCZYK, Matthew GUIDRY
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Publication number: 20250056878Abstract: A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Inventors: Matthew GUIDRY, Brian ROMANCZYK
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Publication number: 20250022948Abstract: An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Inventor: Brian ROMANCZYK
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Patent number: 12183676Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.Type: GrantFiled: January 13, 2023Date of Patent: December 31, 2024Assignee: MONDE WIRELESS INCInventors: Brian Romanczyk, Matthew Guidry
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Patent number: 12132052Abstract: A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.Type: GrantFiled: December 8, 2022Date of Patent: October 29, 2024Assignee: MONDE Wireless, Inc.Inventors: Matthew Guidry, Brian Romanczyk
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Publication number: 20240038761Abstract: A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.Type: ApplicationFiled: December 8, 2022Publication date: February 1, 2024Inventors: Matthew Guidry, Brian Romanczyk
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Patent number: 11699723Abstract: An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.Type: GrantFiled: September 23, 2022Date of Patent: July 11, 2023Assignee: MONDE Wireless Inc.Inventor: Brian Romanczyk
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Publication number: 20230197611Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.Type: ApplicationFiled: January 13, 2023Publication date: June 22, 2023Inventors: Brian Romanczyk, Matthew Guidry
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Patent number: 11594625Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.Type: GrantFiled: February 26, 2020Date of Patent: February 28, 2023Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
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Patent number: 11557539Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.Type: GrantFiled: May 19, 2022Date of Patent: January 17, 2023Assignee: MONDE WIRELESS INC.Inventors: Brian Romanczyk, Matthew Guidry
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Publication number: 20220223429Abstract: N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches.Type: ApplicationFiled: June 18, 2021Publication date: July 14, 2022Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Emmanuel Kayede, Wenjian Liu, Islam Sayed, Umesh K. Mishra
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Publication number: 20210399121Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.Type: ApplicationFiled: June 21, 2021Publication date: December 23, 2021Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Umesh K. Mishra, Pawana Shrestha, Matthew Guidry, James Buckwalter, Stacia Keller, Rohit Reddy Karnaty
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Patent number: 11101379Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.Type: GrantFiled: November 16, 2017Date of Patent: August 24, 2021Assignee: THEREGENIS OF THE UNIVERSITY OF CALIFORNIAInventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra
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Publication number: 20200273974Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.Type: ApplicationFiled: February 26, 2020Publication date: August 27, 2020Applicant: The Regents of the University of CaliforniaInventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
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Publication number: 20190348532Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.Type: ApplicationFiled: November 16, 2017Publication date: November 14, 2019Applicant: The Regents of the University of CaliforniaInventors: Brian Romanczyk, Haoran Li, Elaheh Ahmadi, Steven Wienecke, Matthew Guidry, Xun Zheng, Stacia Keller, Umesh K. Mishra