Abstract: A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal.

Abstract: A video signal processor (1) for converting standard definition and progressive scan video data signals from digital form to analogue form comprises a video signal processing circuit (7) in which the signals are converted. The respective standard and progressive video data signals are received on first and second clock signals CLOCK—1 and CLOCK—2, respectively, which are of identical frequency and have a constant phase relationship. An interface circuit (10) for interfacing the standard definition and progressive scan video data signals with the video signal processor (7) comprises a first register (20) into which the progressive scan signal is clocked on the second clock signal CLOCK—2. The progressive scan signal is clocked from the first register (20) to a second register (21) by the first clock signal CLOCK—1 and in turn from the second register (21) to a third register (22) by the first clock signal CLOCK—1.

Abstract: An extended range of frequency synthesiser responsive to a number of different input frequencies to provide multiples of those input frequencies as its final outputs includes a phase locked loop having an output frequency range containing a multiple of each of the final output frequencies; and a pre-divider circuit for dividing the input frequencies by a first predetermined number before submission to said phase locked loop and a post divider circuit for dividing the phase locked loop output by a second predetermined number to obtain the final output while operating the phase locked loop in the output frequency range.