Patents by Inventor Brian S. Doyle

Brian S. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200251160
    Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 28, 2017
    Publication date: August 6, 2020
    Inventors: ABHISHEK A. SHARMA, RAVI PILLARISETTY, BRIAN S. DOYLE, PRASHANT MAJHI
  • Patent number: 10732217
    Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Kaan Oguz, Christopher J. Wiegand, Mark L. Doczy, Brian S. Doyle, MD Tofizur Rahman, Oleg Golonzka, Tahir Ghani
  • Publication number: 20200243543
    Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 30, 2020
    Inventors: Ravi PILLARISETTY, Abhishek A. SHARMA, Prashant MAJHI, Elijah V. KARPOV, Brian S. DOYLE
  • Publication number: 20200234750
    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Publication number: 20200235221
    Abstract: In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov
  • Publication number: 20200235162
    Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 23, 2020
    Inventors: Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV, Brian S. DOYLE, Abhishek A. SHARMA
  • Publication number: 20200235163
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.
    Type: Application
    Filed: September 14, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Abhishek A. Sharma
  • Publication number: 20200235105
    Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi
  • Publication number: 20200227477
    Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.
    Type: Application
    Filed: September 13, 2017
    Publication date: July 16, 2020
    Inventors: Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV, Brian S. DOYLE, Abhishek A. SHARMA
  • Publication number: 20200220023
    Abstract: An embodiment includes a system comprising: a thin film transistor (TFT) comprising a source, a channel, a drain, and a gate; first, second, and third dielectric portions; wherein (a) a first vertical axis intersects the source, the channel, and the drain; (b) the first dielectric portion surrounds the source in a first plane; (c) the second dielectric portion surrounds the channel in a second plane; (d) the third dielectric surrounds the drain in a third plane; (e) a second vertical axis intersects the first, second, and third dielectric portions; (f) the source includes a first dopant, the first dielectric portion includes the first dopant, the second dielectric portion includes at least one of the first dopant and a second dopant, the drain includes the at least one of the first and second dopants, and the third dielectric portion includes the at least one of the first and second dopants.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 9, 2020
    Inventors: Ravi Pillarisetty, Prashant Majhi, Seung Hoon Sung, Willy Rachmady, Gilbert Dewey, Abhishek A. Sharma, Brian S. Doyle, Jack T. Kavalieros
  • Patent number: 10707409
    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, David L. Kencke, Satyarth Suri, Robert S. Chau
  • Publication number: 20200212105
    Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 2, 2020
    Inventors: Prashant MAJHI, Abhishek A. SHARMA, Elijah V. KARPOV, Ravi PILLARISETTY, Brian S. DOYLE
  • Publication number: 20200212075
    Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.
    Type: Application
    Filed: September 26, 2017
    Publication date: July 2, 2020
    Inventors: Brian S. DOYLE, Abhishek A. SHARMA, Ravi PILLARISETTY, Prashant MAJHI, Elijah V. KARPOV
  • Publication number: 20200176457
    Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.
    Type: Application
    Filed: September 29, 2017
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Publication number: 20200168636
    Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the In topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: September 15, 2017
    Publication date: May 28, 2020
    Inventors: Prashant MAJHI, Brian S. DOYLE, Ravi PILLARISETTY, Abhishek A. SHARMA, Elijah V. KARPOV
  • Publication number: 20200168274
    Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 28, 2020
    Inventors: Ravi PILLARISETTY, Abhishek A. SHARMA, Brian S. DOYLE, Elijah V. KARPOV, Prashant MAJHI
  • Publication number: 20200161473
    Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.
    Type: Application
    Filed: September 17, 2017
    Publication date: May 21, 2020
    Inventors: Prashant MAJHI, Willy RACHMADY, Brian S. DOYLE, Abhishek A. SHARMA, Elijah V. KARPOV, Ravi PILLARISETTY, Jack T. KAVALIEROS
  • Publication number: 20200144293
    Abstract: Ferroelectric field effect transistors (FeFETs) having ambipolar channels are described. In an example, an integrated circuit structure includes a channel layer above a substrate. The channel layer is composed of an ambipolar material. A ferroelectric oxide material is above the channel layer. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 7, 2020
    Inventors: Prashant MAJHI, Brian S. DOYLE, Elijah V. KARPOV, Abhishek A. SHARMA, Ravi PILLARISETTY
  • Publication number: 20200144330
    Abstract: Multi-channel vertical transistors for embedded non-volatile memory are described. In an example, a memory array includes a plurality of non-volatile random access memory (RAM) elements. The memory array also includes a plurality of transistors. Individual ones of the plurality of transistors are coupled to corresponding individual ones of the plurality of non-volatile RAM elements. The plurality of transistors is a plurality of vertical multi-channel transistors.
    Type: Application
    Filed: September 19, 2017
    Publication date: May 7, 2020
    Inventors: Prashant MAJHI, Ravi PILLARISETTY, Abhishek A. SHARMA, Brian S. DOYLE, Elijah V. KARPOV
  • Patent number: 10636960
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz