Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (NC).

Abstract: A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

Abstract: A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing.

Abstract: Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

Abstract: A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer.

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract: A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid.

Abstract: In accordance with the invention, a method for opening holes for semiconductor fabrication includes the steps of providing a pad stack on a substrate, forming a hard mask layer on the pad stack, the hard mask layer selectively removable relative to the pad stack, patterning a resist layer on the hard mask layer, the resist layer being selectively removable relative to the hard mask layer and having a thickness sufficient to prevent scalloping, etching the hard mask layer selective to the resist layer down to the pad stack, removing the resist layer. After removing the resist layer, the pad stack is etched selective to the hard mask layer such that a hole is opened down to the substrate.

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.