Patents by Inventor Brian S. MANTEL

Brian S. MANTEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11181552
    Abstract: A method of classifying waveform data includes receiving input waveform data at a test and measurement system, accessing a repository of reference waveform data and corresponding classes, analyzing the input waveform data and the reference waveform data to designate a class of the input waveform data, and using the class designation to provide information to a user. A test and measurement system has a user interface, at least one input port, a communications port, a processor, the processor configured to execute instructions causing the processor to: receive input waveform data through at least one of the input port or the user interface; access a repository of reference waveform data; analyze the input waveform data using the reference waveform data; designate a class of the input waveform data; and use the class to provide information to the user about the input waveform.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Tektronix, Inc.
    Inventors: Joshua J. O'Brien, Brian S. Mantel
  • Publication number: 20210081592
    Abstract: A method for improving the accuracy of simulation models can include measuring a characteristic value at one or more nodes of a physical embodiment corresponding to the simulation model; inputting the measured characteristic value into a trained machine learning facility corresponding to the simulation model; and receiving from the trained machine learning facility one or more predicted values based at least in part on the inputted measured characteristic value.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 18, 2021
    Inventors: Jonathan S. Dandy, Brian S. Mantel
  • Publication number: 20200166546
    Abstract: A method of classifying waveform data includes receiving input waveform data at a test and measurement system, accessing a repository of reference waveform data and corresponding classes, analyzing the input waveform data and the reference waveform data to designate a class of the input waveform data, and using the class designation to provide information to a user. A test and measurement system has a user interface, at least one input port, a communications port, a processor, the processor configured to execute instructions causing the processor to: receive input waveform data through at least one of the input port or the user interface; access a repository of reference waveform data; analyze the input waveform data using the reference waveform data; designate a class of the input waveform data; and use the class to provide information to the user about the input waveform.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Applicant: Tektronix, Inc.
    Inventors: Joshua J. O'Brien, Brian S. Mantel
  • Patent number: 9007083
    Abstract: A planar body is configured such that its edges engage the sidewall of a via of a device under test to create point electrical contacts and the planar body resists removal of the planar body from the via after insertion. The edges of the planar body may include barbs that create point electrical contacts and resist removal of the planar body from the via after insertion. The end of the body that is inserted into the via may form a tapered tip to facilitate insertion. The end of the planar body that is inserted into the via may include barbs that resist removal of the planar body from the via after insertion. The edges of the planar body may include stops that prevent further insertion of the planar body into the via beyond the stops.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 14, 2015
    Assignee: Tektronix, Inc.
    Inventors: David T. Engquist, Brian S. Mantel
  • Patent number: 8598466
    Abstract: A shielded signal pass-through or via structure integral with an electronic circuit board is described. The structure includes a rigid inner generally cylindrical conductor; at least a semi-rigid intermediate annular dielectric surrounding the conductor; and a rigid outer annular conductor surrounding the dielectric material. Also described is an interconnect device that presents a contact array in a boss region of a unitary embossed printed circuit board (PCB) optionally equipped with one or more such shielded vias.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 3, 2013
    Assignee: Tektronix, Inc.
    Inventors: Brian S. Mantel, David T. Engquist
  • Publication number: 20130033280
    Abstract: A planar body is configured such that its edges engage the sidewall of a via of a device under test to create point electrical contacts and the planar body resists removal of the planar body from the via after insertion. The edges of the planar body may include barbs that create point electrical contacts and resist removal of the planar body from the via after insertion. The end of the body that is inserted into the via may form a tapered tip to facilitate insertion. The end of the planar body that is inserted into the via may include barbs that resist removal of the planar body from the via after insertion. The edges of the planar body may include stops that prevent further insertion of the planar body into the via beyond the stops.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 7, 2013
    Applicant: TEKTRONIX, INC.
    Inventors: David T. ENGQUIST, Brian S. MANTEL
  • Publication number: 20110240347
    Abstract: A shielded signal pass-through or via structure integral with an electronic circuit board is described. The structure includes a rigid inner generally cylindrical conductor; at least a semi-rigid intermediate annular dielectric surrounding the conductor; and a rigid outer annular conductor surrounding the dielectric material. Also described is an interconnect device that presents a contact array in a boss region of a unitary embossed printed circuit board (PCB) optionally equipped with one or more such shielded vias.
    Type: Application
    Filed: January 28, 2011
    Publication date: October 6, 2011
    Applicant: TEKTRONIX, INC.
    Inventors: Brian S. MANTEL, David T. ENGQUIST