Patents by Inventor Brian S. Poarch

Brian S. Poarch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9040386
    Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 26, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Li Li, Amit S. Kelkar, Brian S. Poarch
  • Publication number: 20150028455
    Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.
    Type: Application
    Filed: December 27, 2013
    Publication date: January 29, 2015
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Li Li, Amit S. Kelkar, Brian S. Poarch