Abstract: The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.

Abstract: The present invention, generally speaking, provides for true multi-mode operation enabling mode switching to be done on-the-fly, in real time. Ramping techniques are provided to fully ramp a communications signal down and then back up inside a guard period while switching from one mode to another so that signal glitches occur only while the signal is ramped down and so can be made negligible. In another aspect of the invention, an advantageous multi-mode communications platform having a polar modulation architecture is provided. Preferably, the platform is based on a multi-mode, predominantly digital, single-chip communications signal processor. A digital, phase-stable, frequency lock loop enables versatile, low-power operation.

Abstract: A promotional tool and a vehicle used to distribute products, information, gift certificates, prepaid phone cards, and coupons for businesses, corporations, retail establishments, universities, and sales personnel. A customized gift card displays professionally created artwork, logos and graphics that best portray the provider's intent for the overall design. The card is folded, die-cut and glued to receive a multimedia disc, gift certificate, coupon or phone card. A Multimedia Disc is included as a gift with each card. It is a digital medium that contains professionally recorded digital music and a variety of audio, video, and graphic information regarding the provider. It is placed in the card so the label which supports the card's overall design, is in view. A gift certificate, coupon, or a prepaid phone card can be placed in the card for easy accessibility and scanning by a retailer.

Abstract: A promotional tool and a vehicle used to distribute products, information, gift certificates, pre-paid phone cards, and coupons for businesses, corporations, retail establishments, universities, and sales personnel. A customized gift card displays professionally created artwork, logos and graphics that best portray the provider's intent for the overall design. The card is folded, die-cut and glued to receive a multimedia disc, gift certificate, coupon or phone card. A Multimedia Disc is included as a gift with each card. It is a digital medium that contains professionally recorded digital music and a variety of audio, video, and graphic information regarding the provider. It is placed in the card so the label which supports the card's overall design, is in view. A gift certificate, coupon, or a prepaid phone card can be placed in the card for easy accessibility and scanning by a retailer.

Abstract: A promotional tool and a vehicle used to distribute products, information, gift certificates, prepaid phone cards, and coupons for businesses, corporations, retail establishments, universities, and sales personnel. A customized gift card displays professionally created artwork, logos and graphics that best portray the provider's intent for the overall design. The card is folded, die-cut and glued to receive a multimedia disc, gift certificate, coupon or phone card. A Multimedia Disc is included as a gift with each card. It is a digital medium that contains professionally recorded digital music and a variety of audio, video, and graphic information regarding the provider. It is placed in the card so the label which supports the card's overall design, is in view. A gift certificate, coupon, or a prepaid phone card can be placed in the card for easy accessibility and scanning by a retailer.

Abstract: The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.

Abstract: The present invention, generally speaking, provides a PLL that enables smooth switching of loop bandwidth without changing the loop filter. In accordance with one aspect of the invention, the loop bandwidth of a phase lock loop including an output frequency divider and a reference frequency divider is changed by changing a divisor of the output frequency divider by a factor and changing a divisor of the reference frequency divider by substantially the same factor. If the factor is greater than one, the loop bandwidth is decreased. If the factor is less than one, then the loop bandwidth is increased. In accordance with another aspect of the invention, a phase lock loop includes an oscillator having a control input, a phase comparator, a loop filter, and a feedback path including an output frequency divider. A reference frequency divider is also provided.

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direct modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints.

Abstract: The invented controller uses a programmable parameter scheme which makes it possible to read and write 3 1/2 inch variable and fixed speed drives, as well as standard 5 1/4 inch drives. Additionally, the present invention uses a plus/minus rate multiplier to correct for symmetry and frequency errors. Also provided is a form of read post compensation which corrects for peak shift effects on disks with insufficient precompensation. Other advanced features of the present invention include the use of half clock circuits to provide half clock resolution in the signal being written to and read from the disk and the capability of operating at continuously variable clock speeds and data rates dynamically programmable by the computer.

Abstract: An integrated circuit cell module for performing precise time measurements for use in applications such as disk drive controllers. The combination of the cell module and a hard disk controller chip creates a complete hard disk controller in a single chip without the need for external analog components normally required for classic phase lock loop hard disk controllers. A problem in designing such a unified chip is that it must be digital in nature. Therefore, the maximum resolution with which signals generated by the disk drive (Rddata signals) can be measured and signals generated by the controller for writing to disk (Wrdata signals) can be generated is dependent on the clock which drives the controller chip. In hard disk controllers, the data rate is such that the minimum distance between adjacent Rddata or Wrdata pulses is approximately 100 ns which would require an oscillator having a speed which would be impractical in a design.

Abstract: The invented controller uses a programmable parameter scheme which makes it possible to read and write 31/2 inch variable and fixed speed drives, as well as standard 51/4 inch drives. Additionally, the present invention uses a plus/minus rate multiplier to correct for symmetry and frequency errors. Also provided is a form of read post compensation which corrects for peak shift effects on disks with insufficient precompensation. Other advanced features of the present invention include the use of half clock circuits to provide half clock resolution in the signal being written to and read from the disk and the capability of operating at continuously variable clock speeds and data rates dynamically programmable by the computer.