Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

Abstract: Various techniques are provided for implementing, operating, and manufacturing infrared imaging devices using integrated circuits. In one example, a system includes a focal plane array (FPA) integrated circuit comprising an array of infrared sensors adapted to image a scene, a plurality of active circuit components, a first metal layer disposed above and connected to the circuit components, a second metal layer disposed above the first metal layer and connected to the first metal layer, and a third metal layer disposed above the second metal layer and below the infrared sensors. The third metal layer is connected to the second metal layer and the infrared sensors. The first, second, and third metal layers are the only metal layers of the FPA between the infrared sensors and the circuit components. The first, second, and third metal layers are adapted to route signals between the circuit components and the infrared sensors.

Abstract: An image sensor may be provided. The image sensor may be a high-capacitance image sensor or a dual-mode image sensor having a high-capacitance operational mode. A high-capacitance image sensor may include image detectors and associated unit cells. During operation, the image sensor may integrate image signals from each detector row using unit cells in multiple unit cell rows. The image sensor may integrate and readout image signals in an interleaved process that allows each detector row to capture image data using multiple unit cells. A dual-mode image sensor may operate in a similar manner to a high-capacitance image sensor when operated in the high-capacitance mode. The dual-mode image sensor may have switches interposed between unit cells to selectively couple and decouple the unit cells for switching between the high-capacitance mode and a normal operational mode.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: An image sensor may be provided. The image sensor may be a high-capacitance image sensor or a dual-mode image sensor having a high-capacitance operational mode. A high-capacitance image sensor may include image detectors and associated unit cells. During operation, the image sensor may integrate image signals from each detector row using unit cells in multiple unit cell rows. The image sensor may integrate and readout image signals in an interleaved process that allows each detector row to capture image data using multiple unit cells. A dual-mode image sensor may operate in a similar manner to a high-capacitance image sensor when operated in the high-capacitance mode. The dual-mode image sensor may have switches interposed between unit cells to selectively couple and decouple the unit cells for switching between the high-capacitance mode and a normal operational mode.

Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Abstract: Various techniques are provided for implementing, operating, and manufacturing infrared imaging devices using integrated circuits. In one example, a system includes a focal plane array (FPA) integrated circuit comprising an array of infrared sensors adapted to image a scene, a plurality of active circuit components, a first metal layer disposed above and connected to the circuit components, a second metal layer disposed above the first metal layer and connected to the first metal layer, and a third metal layer disposed above the second metal layer and below the infrared sensors. The third metal layer is connected to the second metal layer and the infrared sensors. The first, second, and third metal layers are the only metal layers of the FPA between the infrared sensors and the circuit components. The first, second, and third metal layers are adapted to route signals between the circuit components and the infrared sensors.