Patents by Inventor Brian Sprague

Brian Sprague has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160198221
    Abstract: One or more circuits for use in a transceiver that is collocated with a satellite dish, may receive a satellite signal carrying media content, and remove content protection from the received media content. After removing the first content protection, the one or more circuits may apply second content protection to the media content. The content protection applied by the one or more circuits may adhere to a different protocol, utilize different keys, and/or otherwise be distinguishable from the content protection that was removed. After applying the content protection, the one or more circuits may transmit the media content onto one or more links between the satellite dish and one or more client devices. The removal of the content protection may comprise descrambling and/or decrypting the media content. The application of the content protection may comprise scrambling and/or encrypting the media content.
    Type: Application
    Filed: August 31, 2015
    Publication date: July 7, 2016
    Inventors: Brian Sprague, Glenn Chang, Timothy Gallagher, Sridhar Ramesh
  • Publication number: 20150310077
    Abstract: Various methods and apparatuses are described for performing high speed translations of data. In an example embodiment, record layout detection can be performed for data. In another example embodiment, data pivoting prior to field-specific data processing can be performed.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 29, 2015
    Inventors: Joseph M. Lancaster, Michael John Henrichs, Terry Tidwell, Alex St. John, Kevin Brian Sprague
  • Publication number: 20150310078
    Abstract: Various methods and apparatuses are described for performing high speed translations of data. In an example embodiment, record layout detection can be performed for data. In another example embodiment, data pivoting prior to field-specific data processing can be performed.
    Type: Application
    Filed: April 23, 2015
    Publication date: October 29, 2015
    Inventors: Joseph M. Lancaster, Kevin Brian Sprague
  • Patent number: 9124925
    Abstract: One or more circuits for use in a transceiver that is collocated with a satellite dish, may receive a satellite signal carrying media content, and remove content protection from the received media content. After removing the first content protection, the one or more circuits may apply second content protection to the media content. The content protection applied by the one or more circuits may adhere to a different protocol, utilize different keys, and/or otherwise be distinguishable from the content protection that was removed. After applying the content protection, the one or more circuits may transmit the media content onto one or more links between the satellite dish and one or more client devices. The removal of the content protection may comprise descrambling and/or decrypting the media content. The application of the content protection may comprise scrambling and/or encrypting the media content.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 1, 2015
    Assignee: MaxLinear, Inc.
    Inventors: Brian Sprague, Glenn Chang, Timothy Gallagher, Sridhar Ramesh
  • Publication number: 20150026736
    Abstract: A satellite reception assembly may comprise a housing configured to support receipt and handling of a plurality of satellite signals. The housing may comprise circuitry incorporating integrated stacking architecture for supporting and/or providing channel and/or band stacking whereby particular channels or bands, from multiple satellite signals that are received via the satellite reception assembly, may be combined onto a single output signal that may be communicated from the satellite reception assembly to a gateway device for concurrent distribution thereby to a plurality of client devices serviced by the gateway device.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 22, 2015
    Inventors: Glenn Chang, Brian Sprague, Madhukar Reddy
  • Patent number: 8799964
    Abstract: A satellite reception assembly may comprise a housing configured to support receipt and handling of a plurality of satellite signals. The housing may comprise circuitry incorporating integrated stacking architecture for supporting and/or providing channel and/or band stacking whereby particular channels or bands, from multiple satellite signals that are received via the satellite reception assembly, may be combined onto a single output signal that may be communicated from the satellite reception assembly to a gateway device for concurrent distribution thereby to a plurality of client devices serviced by the gateway device.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 5, 2014
    Assignee: MaxLinear, Inc.
    Inventors: Glenn Chang, Brian Sprague, Madhuka Reddy
  • Publication number: 20140114908
    Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 24, 2014
    Inventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
  • Publication number: 20140114929
    Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 24, 2014
    Inventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
  • Publication number: 20130205349
    Abstract: A satellite reception assembly may comprise a housing configured to support receipt and handling of a plurality of satellite signals. The housing may comprise circuitry incorporating integrated stacking architecture for supporting and/or providing channel and/or band stacking whereby particular channels or bands, from multiple satellite signals that are received via the satellite reception assembly, may be combined onto a single output signal that may be communicated from the satellite reception assembly to a gateway device for concurrent distribution thereby to a plurality of client devices serviced by the gateway device.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 8, 2013
    Inventors: Glenn Chang, Brian Sprague, Madhukar Reddy
  • Publication number: 20120297415
    Abstract: A network device may pair with a particular satellite dish by storing a security key uniquely associated with the particular satellite dish. The network device may then receive encrypted data from the particular satellite dish, and decrypt the received encrypted data utilizing the security key. One or more circuits of the network device may be operable to prevent the network device from decrypting data from any satellite dish other than the particular satellite dish. The network device may be operable such that the security key is the only key that the network device can utilize for decrypting signals received via a particular interface and/or from a particular address. One or more circuits collocated with a satellite dish may be operable to encrypt data utilizing a security key stored in the one or more circuits. The security key may be unique to the one or more circuits and/or satellite dish.
    Type: Application
    Filed: January 20, 2012
    Publication date: November 22, 2012
    Inventors: Brian Sprague, Curtis Ling
  • Publication number: 20120297414
    Abstract: One or more circuits for use in a transceiver that is collocated with a satellite dish, may receive a satellite signal carrying media content, and remove content protection from the received media content. After removing the first content protection, the one or more circuits may apply second content protection to the media content. The content protection applied by the one or more circuits may adhere to a different protocol, utilize different keys, and/or otherwise be distinguishable from the content protection that was removed. After applying the content protection, the one or more circuits may transmit the media content onto one or more links between the satellite dish and one or more client devices. The removal of the content protection may comprise descrambling and/or decrypting the media content. The application of the content protection may comprise scrambling and/or encrypting the media content.
    Type: Application
    Filed: December 12, 2011
    Publication date: November 22, 2012
    Inventors: Brian Sprague, Glenn Chang, Timothy Gallagher, Sridhar Ramesh
  • Patent number: 7233778
    Abstract: An apparatus for converting a signal from a first analog format to a second analog format. The apparatus has an input port, a first converter, filters, first mixers, second converters, and an output port. The input port is configured to receive the signal. The signal has the first analog format. In an embodiment, the first analog format complies with the SCTE 40 2003 technical standard. In an embodiment, the second analog format is a conventional analog format. The first converter is coupled to the port and is configured to convert the signal to a first digital format. The filters are coupled to the first converter and configured to isolate a first channel of the signal from a second channel of the signal. The first mixers are coupled to the filters and configured to expand the first channel and the second channel to a second digital format. The second converters are coupled to the first mixers and configured to convert the first channel and the second channel to the second analog format.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: June 19, 2007
    Assignee: Broadcom Corporation
    Inventors: Richard Nelson, Brian Sprague, Donald McMullin, Richard Prodan, Pieter Vorenkamp
  • Patent number: 6980712
    Abstract: Methods of calibrating and operating optical switches as well as optical switches in which the orientations of mirrors are measured and controlled using control light beams and position sensing detectors are described. The present invention may provide high resolution control of a plurality of mirrors in an optical switch and thus allow the optical switch to cross-connect a large number of input and output ports with a low insertion loss.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: December 27, 2005
    Assignee: Intel Corporation
    Inventors: Cheng-Chung Huang, Steven Saeed Nasiri, Randall Brian Sprague, Alex Harwit, Dmitry Vasily Bakin, Janusz Bryzek
  • Patent number: 6952003
    Abstract: An apparatus for detecting a centroid of a spot produced by electromagnetic radiation, e.g., optic radiation, using an array of PIN photodiodes serving as photodetectors and being organized in columns and in rows. Vertical connections are used to interconnect the PIN photodiodes in the columns in accordance with a first pattern that interconnects two or more adjacent columns. Horizontal connections are used to interconnect PIN photodiodes in the rows in accordance with a second pattern that interconnects two or more adjacent rows. The first and second patterns of interconnections can include just two adjacent columns and two adjacent rows, respectively and form a checkerboard interconnect pattern. The interconnections are made such that there are no anode connections between the PIN photodiodes in the rows and columns.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: David Skurnik, Randall Brian Sprague, Geoffrey Hugh Jones, Eric Charles Abbott, Waisiu Law
  • Patent number: 6922500
    Abstract: An optical fiber switch in accordance with an embodiment of the present invention includes a first plurality of ports, a second plurality of ports, a first plurality of mirrors disposed on a first surface, and a second plurality of mirrors disposed on a second surface. Each one of the first plurality of mirrors is individually controllable to direct light output from a corresponding one of the first plurality of ports to any one of the second plurality of mirrors. Each one of the second plurality of mirrors is individually controllable to direct to a corresponding one of the second plurality of ports light incident on it from any one of the first plurality of mirrors. Advantageously, optical fiber switches in accordance with embodiments of the present invention may couple more than a thousand input ports to more than a thousand output ports with an insertion loss of less than about 3 decibels.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: July 26, 2005
    Assignee: Intel Corporation
    Inventors: Cheng-Chung Huang, Steven Saeed Nasiri, Randall Brian Sprague, Alex Harwit, Dmitry Vasily Bakin, Janusz Bryzek
  • Patent number: 6898341
    Abstract: Methods of calibrating and operating optical switches as well as optical switches in which the orientations of mirrors are measured and controlled using control light beams and position sensing detectors are described. The present invention may provide high resolution control of a plurality of mirrors in an optical switch and thus allow the optical switch to cross-connect a large number of input and output ports with a low insertion loss.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Cheng-Chung Huang, Steven Saeed Nasiri, Randall Brian Sprague, Alex Harwit, Dmitry Vasily Bakin, Janusz Bryzek
  • Publication number: 20050020222
    Abstract: An apparatus for tuning a frequency conversion device. The apparatus has a channel identifier, a channel cross-referencer, and a frequency conversion device tuner. The channel identifier is configured to identify a first channel to which a receiver is tuned. The channel cross-referencer is coupled to the channel identifier and is configured to cross-reference the first channel with a second channel. The frequency conversion device tuner is coupled to the channel cross-referencer and is configured to tune the frequency conversion device to the second channel. An apparatus for processing a signal. The apparatus has an input port, a signal format identifier, a switch, a converter, an output port, and a bypass signal path. The input port is configured to receive the signal. The signal format identifier is coupled to the input port and configured to identify the signal as having a first format or a second format. The switch is coupled to the signal format identifier.
    Type: Application
    Filed: May 27, 2004
    Publication date: January 27, 2005
    Applicant: Broadcom Corporation
    Inventors: Richard Nelson, Brian Sprague, Donald McMullin, Richard Prodan, Pieter Vorenkamp
  • Publication number: 20050017882
    Abstract: An apparatus for converting a signal from a first analog format to a second analog format. The apparatus has an input port, a first converter, filters, first mixers, second converters, and an output port. The input port is configured to receive the signal. The signal has the first analog format. In an embodiment, the first analog format complies with the SCTE 40 2003 technical standard. In an embodiment, the second analog format is a conventional analog format. The first converter is coupled to the port and is configured to convert the signal to a first digital format. The filters are coupled to the first converter and configured to isolate a first channel of the signal from a second channel of the signal. The first mixers are coupled to the filters and configured to expand the first channel and the second channel to a second digital format. The second converters are coupled to the first mixers and configured to convert the first channel and the second channel to the second analog format.
    Type: Application
    Filed: May 27, 2004
    Publication date: January 27, 2005
    Applicant: Broadcom Corporation
    Inventors: Richard Nelson, Brian Sprague, Donald McMullin, Richard Prodan, Pieter Vorenkamp
  • Patent number: 6831263
    Abstract: An apparatus for detecting a centroid of a spot produced by electromagnetic radiation, e.g., optic radiation, using an array of PIN photodiodes serving as photodetectors and being organized in columns and in rows. Vertical connections are used to interconnect the PIN photodiodes in the columns in accordance with a first pattern that interconnects two or more adjacent columns. Horizontal connections are used to interconnect PIN photodiodes in the rows in accordance with a second pattern that interconnects two or more adjacent rows. The first and second patterns of interconnections can include just two adjacent columns and two adjacent rows, respectively and form a checkerboard interconnect pattern. The interconnections are made such that there are no anode connections between the PIN photodiodes in the rows and columns.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: December 14, 2004
    Assignee: Intel Corporation
    Inventors: David Skurnik, Randall Brian Sprague, Geoffrey Hugh Jones, Eric Charles Abbott, Waisiu Law
  • Publication number: 20030222200
    Abstract: An apparatus for detecting a centroid of a spot produced by electromagnetic radiation, e.g., optic radiation, using an array of PIN photodiodes serving as photodetectors and being organized in columns and in rows. Vertical connections are used to interconnect the PIN photodiodes in the columns in accordance with a first pattern that interconnects two or more adjacent columns. Horizontal connections are used to interconnect PIN photodiodes in the rows in accordance with a second pattern that interconnects two or more adjacent rows. The first and second patterns of interconnections can include just two adjacent columns and two adjacent rows, respectively and form a checkerboard interconnect pattern. The interconnections are made such that there are no anode connections between the PIN photodiodes in the rows and columns.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 4, 2003
    Inventors: David Skurnik, Randall Brian Sprague, Geoffrey Hugh Jones, Eric Charles Abbott, Waisiu Law