Patents by Inventor Brian Stoner

Brian Stoner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200282096
    Abstract: The present invention provides devices, systems and methods for electrochemically modulating functional groups associated with a specific odorant molecule for purposes of altering the smell associated with the specific odorant molecule.
    Type: Application
    Filed: November 13, 2018
    Publication date: September 10, 2020
    Inventors: Edgard NGABOYAMAHINA, Claire DE MARCH, Jeffrey GLASS, Brian STONER, Hiroaki MATSUNAMI
  • Patent number: 9136794
    Abstract: An apparatus, system, and method are disclosed for modulating electric current. An electron source electrode provides a flow of electrons in a partial vacuum environment. An ionizable gas in the partial vacuum environment forms positively charged ion particles in response to impact with the electrons from the electron source electrode. Application of a bias voltage differential between a first bias electrode and a second bias electrode in the partial vacuum environment forms an electric field gradient in a path of the flow of electrons. A collector electrode in the partial vacuum environment collects more electrons than ion particles when a collector electrode input voltage is above a threshold, and collects more ion particles than electrons when the collector electrode input voltage is below the threshold.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: September 15, 2015
    Assignee: Research Triangle Institute, International
    Inventors: Brian Stoner, Jeffrey Piascik
  • Publication number: 20140104013
    Abstract: An apparatus, system, and method are disclosed for modulating electric current. An electron source electrode 202 provides a flow of electrons in a partial vacuum environment 116. An ionizable gas 118 in the partial vacuum environment 116 forms positively charged ion particles in response to impact with the electrons from the electron source electrode 202. Application of a bias voltage differential between a first bias electrode 204 and a second bias electrode 206 in the partial vacuum environment 116 forms an electric field gradient in a path of the flow of electrons. A collector electrode 208 in the partial vacuum environment 116 collects more electrons than ion particles when a collector electrode input voltage 106 is above a threshold, and collects more ion particles than electrons when the collector electrode input voltage 106 is below the threshold.
    Type: Application
    Filed: June 21, 2012
    Publication date: April 17, 2014
    Applicant: RESEARCH TRIANGLE INSTITUTE, INTERNATIONAL
    Inventors: Brian Stoner, Jeffrey Piascik
  • Publication number: 20040201095
    Abstract: An improved through-via vertical interconnect, through-via heat sinks and associated fabrication techniques are provided for. The devices benefit from an organic dielectric layer that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.
    Type: Application
    Filed: April 29, 2004
    Publication date: October 14, 2004
    Applicant: MCNC
    Inventors: William Devereux Palmer, Salvature Bonafede, Dorota Temple, Brian Stoner
  • Publication number: 20030038344
    Abstract: An improved through-via vertical interconnect, through-via heat sinks and associated fabrication techniques are provided for. The devices benefit from an organic dielectric layer that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 27, 2003
    Applicant: MCNC
    Inventors: William Devereux Palmer, Salvatore Bonafede, Dorota Temple, Brian Stoner