Abstract: A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the background, thereby reducing bus idle time.

Abstract: A post write buffer for a dual clock system which improves the utilization of host data bus (10) bandwidth is provided which consists of an address buffer (60), a data buffer (62), a first clock timing signal (22), a second clock timing signal (48), an address decoder (24), a first write enable circuit (72), and a second write enable circuit (74). The address-buffer (60) and data buffer (62). hold the data and the destination address for that data until the clock signals are synchronized and the data is ready for transfer. The address decoder (24) determines which destination register byte will receive the data in the host data bus (10). The write enable circuits (72, 74) synchronize the clock signals (22, 48) and determine when the destination register is ready to receive the data from the data buffer (62).

Abstract: An improved counter register (30) and method of transferring data from a host data bus (29) controlled by a first clock source (BCLK) to the cycle timer (18) controlled by a second clock source (NCLK) which frees the host data bus (29) to perform other functions while a clock synchronization process occurs to allow the data (24) to be written to the counter register (30) or read from the counter register (30). This synchronization scheme is such that at any time the host data bus (29) may read data (25) from the cycle timer (18) and retrieve the current counter register value. In the alternative, at any time, the host data bus (29) may write to the cycle timer (18) and it will receive this data (24) immediately. In either case, the data is transferred immediately without the host data bus (29) having to wait for synchronization across the aforementioned clock boundary.

Abstract: A method for reading data from an IEEE 1394 serial bus system and storing the data in a FIFO includes partitioning the FIFO into a plurality of registers, each having 32 register bits for the data and a single register bit for a control data bit. To manipulate the system such that reads on a data quadlet involve only one system read on a 32-bit system, a packet token is stored in the initial register in a data packet. This packet token includes the quadlet count in the data packet. The host system need only read the first register in the data packet, the packet token, to determine the number of data quadlets within the data packet. Thereafter, the control data bit need not be read such that only a single read operation is performed for each operation of the read pointer. The last register associated with the packet is the acknowledge register which contains information that is sent back to the transmit node in the system.

Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

Abstract: A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A PAL (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The PAL utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating "protocol overhead" timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.

Abstract: A method and apparatus for a circuit physically realizing a Universal Asynchronous Receive/Transmit (UART) circuit 31, 40 having an automatic flow control feature. A preferred embodiment includes a UART 31 provided with additional control circuitry 39, 34 for automatically pausing transfers from the transmit data circuitry 35, 32 in response to a transition at the CTS (Clear to Send) input, and further provided with control circuitry 39 for automatically asserting and deasserting a RTS (Ready to Send) output when a receiver data threshold is reached.

Abstract: A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and "live-lock" conditions.

Abstract: A bus interface system includes a processor unit 10 a local bus 11 coupled to the processor unit and interface circuitry 12 coupled to the local bus 11 for providing continuous generation of addresses on the local bus 11 or on a system bus 15. The local bus 11 may be a processor bus on a computer board while the system bus 15 may be an architectural bus standard such as Futurebus+. The interface circuitry 12 includes a universal address generator 14 that provides proper address generation on both system bus 15 and local bus 11. Also a method of generating addresses includes loading an address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step.