Abstract: An improved full screen view user interface is provided that presents a user interface-light reading mode for reading a document, and a user interface-light editing mode for editing or authoring a document. A full screen view reading mode provides a full page reading environment that simulates real world effects, such as page curls, to enhance a reading experience that is intended to be focused on the task of reading a document. A full screen editing mode provides a full page editing environment that, upon demand, reveals selectable controls that are relevant to editing or authoring a document to provide a simplified, non-distracting writing environment.

Abstract: Embodiments of the present invention provide a design that employs a system of tabs that have parent-child relationships. Within each tab, compartments containing selectable functionality controls may be included, wherein the compartments are logically and systematically arranged to map to the tabs under which they fall, and are shown in an order that reflects the designer's intent of priority and frequency of use.

Abstract: Methods of recovering symbols and corresponding communication receivers including dual receivers configured to perform the method, where the method comprises: sampling a received signal that includes interference to provide received samples; determining a plurality of high power symbols and determining alternate symbols for a portion of the plurality of high power symbols based on the received samples and based on known training symbols; and deriving a sequence of recovered symbols corresponding to the received samples based on the received samples and augmented training symbols, the augmented training symbols comprising the known training symbols augmented by the plurality of high power symbols with one or more alternate symbols replacing a corresponding one or more high power symbols.

Abstract: A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom.

Abstract: Methods of recovering symbols and corresponding communication receivers including dual receivers configured to perform the method, where the method comprises: sampling a received signal that includes interference to provide received samples; determining a plurality of high power symbols and determining alternate symbols for a portion of the plurality of high power symbols based on the received samples and based on known training symbols; and deriving a sequence of recovered symbols corresponding to the received samples based on the received samples and augmented training symbols, the augmented training symbols comprising the known training symbols augmented by the plurality of high power symbols with one or more alternate symbols replacing a corresponding one or more high power symbols.

Abstract: A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom.

Abstract: Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.

Abstract: Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.

Abstract: A radio receiver circuit (200) is used for receiving a multi-level signal (201) that includes a plurality of symbols, wherein each level is representative of a symbol of data. Baseband samples are generated for each symbol, whereby each baseband sample has a phase and a signal level. The radio receiver circuit (200) measures the received signal environment. A digital circuit (212) selects a scan duration from a scan duration table (251) based on the measured signal environment and a combination of signal types used for classification of the received signal. The digital circuit tallies, by category, occurrences of the baseband samples, whereby each category is representative of one of a plurality of phases, and one of a plurality of signal level ranges.

Abstract: A digital signal processor having a multiplierless computation block (140) is accomplished by storing approximations of computed logarithms in memory (160, 162). When two pieces of data (114, 116) are received, the approximate logarithms, or logarithmic data (120, 128), for each of the pieces data are retrieved from memory. The logarithmic data (120, 128) is them summed to produce a resultant (136), wherein the resultant (136) is used to retrieve an inverse logarithmic approximation (180) that is stored in memory (170, 172) in a manner similar to that of the logarithmic approximations. The inverse logarithmic approximation (180) that results closely approximates the product of multiplying, or another arithmetic function, the two pieces of data (114, 116).

Abstract: A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).