Patents by Inventor Brian T. Waldron

Brian T. Waldron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190207694
    Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Applicant: Schweitzer Engineering Laboratories, Inc.
    Inventors: David J. Dolezilek, Jorge Fernando Calero, Amandeep Singh Kalra, Brian T. Waldron
  • Patent number: 10298343
    Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 21, 2019
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: David J. Dolezilek, Jorge Fernando Calero, Amandeep Singh Kalra, Brian T. Waldron
  • Publication number: 20180254994
    Abstract: The present disclosure pertains to systems and methods for publishing time-synchronized information. In one embodiment, a system may include a time interface configured to receive a common time signal and a network interface configured to transmit a plurality of data packets using a network. A publishing subsystem may be configured to cause the system to publish at least one data value according to a schedule and the common time signal. A processing sequence number subsystem may be configured to generate a processing sequence number to be included in the plurality of data packets and to reset the processing sequence number at a fixed interval based on the common time signal. A data packet subsystem may be configured to generate a plurality of data packets comprising a respective processing sequence number and the at least one data value.
    Type: Application
    Filed: March 3, 2017
    Publication date: September 6, 2018
    Applicant: Schweitzer Engineering Laboratories, Inc.
    Inventors: David J. Dolezilek, Jorge Fernando Calero, Amandeep Singh Kalra, Brian T. Waldron