Abstract: A method for forming semiconductor devices with spacers is provided. SiCO spacers are formed on sides of features. Protective coverings are formed over first parts of the SiCO spacers, wherein second parts of the sidewalls of the SiCO spacers are not covered by the protective coverings. A conversion process is provided to the second parts of the SiCO spacers which are not covered by the protective coverings, which changes a physical property of the second parts of the SiCO spacers which are not covered by the protective coverings, wherein the protective coverings protects the first parts of the SiCO spacers from the conversion process.

Abstract: A method for forming semiconductor devices with spacers is provided. SiCO spacers are formed on sides of features. Protective coverings are formed over first parts of the SiCO spacers, wherein second parts of the sidewalls of the SiCO spacers are not covered by the protective coverings. A conversion process is provided to the second parts of the SiCO spacers which are not covered by the protective coverings, which changes a physical property of the second parts of the SiCO spacers which are not covered by the protective coverings, wherein the protective coverings protects the first parts of the SiCO spacers from the conversion process.

Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Abstract: Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.

Abstract: Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a latter deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.

Abstract: Disclosed is a method and structure where a first spacer is formed and an NFET is implanted, and then a second spacer is formed and a PFET is implanted. A dry nitride etch is then performed which selectively removes the second spacer, stopping selectively on an etch stop. This all dry removal process is more manufacturable than a wet etch, since it can be controlled to etch at a slower rate and it is not isotropic. This leaves a double nitride spacer on the PFETs and a single nitride spacer on the NFETs, giving the optimal spacer for each type of device. Furthermore, before suicide formation, the etch stop film on the nitride is removed, leading to a silicide edge very close to the gates for the NFETs, which is optimum for NFETs. The double nitride spacer on the PFETs prevents the silicide from getting too close to the PFET gate, which is optimum for PFETs.