Abstract: A frequency offset estimator (400) and corresponding method (600) provides a frequency offset estimate (415) for an OFDM signal. The estimator comprises a data parser (403) coupled to an input signal (401) and arranged to select a group of symbols (305-311) or corresponding samples corresponding to predetermined symbols from the input signal and a processor (405) arranged to provide a correlation corresponding to the symbols, where the correlation corresponds to a frequency offset estimation for the input signal and is determined in a sequential fashion so that the correlation is provided concurrently with the last symbol or sample of the group of symbols to be selected.

Abstract: A decorrelating rake receiver (401) using a signal processor (213) and corresponding method (1000) to determine filter coefficients (1005). The decorrelating rake receiver includes a plurality of filters (219) arranged to be coupled to an input signal (403) and the filter coefficients (409), the plurality of filters operable to provide a plurality of output signals and a coefficient generator (407), coupled to the input signal, to explicitly and definitely determine the filter coefficients for the plurality of filters such that the plurality of filters perform a decorrelating rake process. The decorrelating rake receiver further includes a combiner (221) to combine the plurality of output signals and provide a received signal (405). The decorrelating rake receiver (401) is suitable for use in a wireless communication device (101) or base transceiver (103).

Abstract: A method and apparatus (400) process a composite signal (202) comprising a spread spectrum signal and an interfering signal (204) to determine the center frequency of the interfering signal, and to shift the composite signal by an amount determined from the characteristic frequency of the interfering signal, thereby creating a shifted composite signal (146) in which the frequency of the interfering signal is a predetermined frequency. The method and apparatus then filters the shifted composite signal to remove the interfering signal, thereby creating an interference-free shifted signal (148), and reshifts the interference-free shifted signal by the amount determined from the characteristic frequency of the interfering signal, thereby recovering the desired spread spectrum signal.

Abstract: A mixer (200, 201) including a transformation circuit (210) is used for frequency converting a first digital signal (208), sampled at a first sampling rate and operating at a first frequency, to a second digital signal (214) operating at a desired frequency. The transformation circuit (210) is adapted to modify and filter the first digital signal (208) to eliminate unwanted frequencies in the first digital signal (208) and to alter the first sampling rate of the first digital signal (208) by a predetermined factor to generate a modified and filtered first digital signal (308) operating at a second sampling rate and the first frequency. The transformation circuit (210) is further adapted to mix the modified and filtered first digital signal (308) with a predetermined injection signal (312) to generate the second digital signal (214) operating at the desired frequency and the second sampling rate.

Abstract: An automatic frequency control circuit (84) and a method for automatic frequency control in a digital receiver includes a CORDIC vector rotation processor (88), an FM demodulator (100) and an integrator (72). The circuit and method utilize the CORDIC computing technique to simplify required circuitry and to reduce required software processing power over conventional automatic frequency control techniques.

Abstract: A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corresponding one of the P current accumulated operands is stored in each of the P operand registers (582) in place of one of the P partial accumulated operands in response to the iteration. Each of P feedback paths (593) couples one of P outputs of the P operand registers (582) to a corresponding one of P feedback inputs of the multiply accumulate reduction circuit (527). An adder (561) that is coupled to the P outputs through isolation circuits (570) generates an output (551) in N iterations that is a sum of N products, each being a product of one of a series of N multipliers and one of a series of N multiplicands.