Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.

Abstract: Methods and apparatuses for locating cloned CPEs in a communication system are provided. A clone detector receives from each access router in a communication system the MAC addresses of CPEs registered with the access router. The clone detector compares the MAC addresses to identify a cloned MAC address. The clone detector determines the service address for the cloned MAC address and identifies neighboring CPEs to the service address. The clone detector determines the access router to which the neighboring CPEs are registered and identifies a CPE having the cloned MAC address and registered to any other access router than the access router to which the neighboring CPEs are registered as a cloned CPE.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: Methods and apparatuses for locating cloned CPEs in a communication system are provided. A clone detector receives from each access router in a communication system the MAC addresses of CPEs registered with the access router. The clone detector compares the MAC addresses to identify a cloned MAC address. The clone detector determines the service address for the cloned MAC address and identifies neighboring CPEs to the service address. The clone detector determines the access router to which the neighboring CPEs are registered and identifies a CPE having the cloned MAC address and registered to any other access router than the access router to which the neighboring CPEs are registered as a cloned CPE.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.