Abstract: A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.

Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serve as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.

Abstract: A cache eviction algorithm for an inclusive cache determines which among a plurality of cache lines may be evicted from the inclusive cache based at least in part upon the state of the cache lines in a higher level cache. In particular, a cache eviction algorithm may determine, from an inclusive cache directory for a lower level cache, whether a cache line is cached in the lower level cache but not cached in any of a plurality of higher level caches for which cache directory information is additionally stored in the cache directory. Then, based upon determining that a cache line is cached in the lower level cache but not cached in any of the plurality of higher level caches, the cache eviction algorithm may select that cache line for eviction from the cache.

Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

Abstract: In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.

Abstract: In a first aspect, a first method is provided for processing commands on a bus. The first method includes the steps of (1) in a first phase of bus command processing, receiving a new command from a processor in a memory controller via the bus, wherein a command on the bus is processed in a plurality of sequential phases; (2) starting to perform memory controller tasks the results of which are required by a second phase of bus command processing; (3) before performing the second phase of bus command processing on the new command, determining whether there are any pending commands previously received in the memory controller that should complete before the second phase of processing is performed on the new command; and (4) if not, performing the second phase of processing on the new command without requiring the memory controller to insert a processing delay on the bus. Numerous other aspects are provided.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.