Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

Abstract: Embodiments of the present disclosure are directed to methods, systems, and computer program products for implementing spare ECO cell coverage validation within an IC) layout. A disclosed embodiment enables spare ECO cell coverage validation using density-based Design Rule Checking (DRC) techniques for validating both a minimum quantity and effective distribution of spare ECO cells in a given IC layout, effectively and efficiently providing ECO cell coverage verification, and accurately identifying failing spare ECO cell coverage. Disclosed embodiments automate the process of validating both a threshold or sufficient spare cell quantity and effective distribution of the spare ECO cells within an IC design layout.

Abstract: A hierarchical integrated circuit design includes at least an upper hierarchy level, an intermediate hierarchy level, and a lower hierarchy level. The lower hierarchy level includes a design entity including an antenna diode. Processing circuitry of a data processing system performs placement for integrated circuitry bounded by the design entity.

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level.

Abstract: A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level.