Abstract: A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.

Abstract: An improved memory system and memory controller which permits simplified memory upgrades in the field. The system includes a memory board with multiple card sockets. As additional cards are added the data cables are distributed among the cards and the memory controller is programmed to coordinate the sequencing of the memory in the cards. Data is transferred between the cards and memory controller via distributively coupled cables. Control and address signals are provided to cards via wires embedded in the memory board from the memory controller. A repowering circuit on each card makes copies of the control and address signals which are sent to other cards through the embedded wires in the board. Data received by a card is stored in memory through steering logic and buffers.

Abstract: A programmable memory controller generates address and control signal information associated with a word of data which is desired to be transferred first from dynamic random access memory (DRAM) modules. The generated information specifically assists memory support circuitry interfacing with page mode DRAMs. This information is normally provided to the memory support circuitry just before selection of the staring word from a fetch line data buffer. Memory latency, gaps in data transfer, can be reduced when this information is available to the support circuitry as it drives column address and/or column address strobe (CAS) signals to the DRAMs.

Abstract: An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.