Abstract: Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.

Abstract: Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.

Abstract: A system for detecting a jack configuration comprising a first plurality of switches configured to couple a first headphone jack position to ground. A second plurality of switches configured to couple a second headphone jack position to ground. A microphone bias circuit for applying a microphone bias signal to the second headphone jack position when the first headphone jack position is coupled to ground, and for applying the microphone bias signal to the first headphone jack position when the second headphone jack position is coupled to ground.

Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.

Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.

Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Abstract: A system for detecting a jack configuration comprising a first plurality of switches configured to couple a first headphone jack position to ground. A second plurality of switches configured to couple a second headphone jack position to ground. A microphone bias circuit for applying a microphone bias signal to the second headphone jack position when the first headphone jack position is coupled to ground, and for applying the microphone bias signal to the first headphone jack position when the second headphone jack position is coupled to ground.

Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Abstract: A circuit for implementing a first order noise shaping apparatus for use in data converters employing thermometer-code based elements is disclosed. Raw thermometer code is rotated by up to four columns of shifters such that the code is rotated up to 15 positions. In this manner, the elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements. Such a process may be used in digital to analog converters and analog to digital converters such that a suitable data weighted algorithm can be used.