Patents by Inventor Brian W. Kernighan

Brian W. Kernighan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5953006
    Abstract: Interactive Methods and apparatus for studying similarities of values in very large data sets. The methods and apparatus employ a dotplot in an interactive graphical user interface to make the relationship between the similarities and the data set visible. A variety of filtering, weighting, and compression techniques make it possible to employ the dot plot with sequences of more than 10,000 tokens and to interactively magnify the dot plot, change weighting and display quantization, and view the underlying data. Also disclosed is a technique which is employed in the apparatus for identifying long sequences of similar tokens. The apparatus is used in the study of large bodies of text and code.
    Type: Grant
    Filed: March 18, 1992
    Date of Patent: September 14, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Brenda Sue Baker, Kenneth Ward Church, Jonathan Isaac Helfman, Brian W. Kernighan
  • Patent number: 5450615
    Abstract: Techniques are disclosed for predicting RF propagation within a structure such as a building. A reference transmitter location and a plurality of reference receiver locations are selected. For each reference receiver location, RF propagation pathways are determined with respect to the reference transmitter location. The RF propagation pathways include a direct path joining the reference transmitter location to a given reference receiver location across a straight-line path, as well as one or more reflection paths joining the reference transmitter location to a given reference receiver location via reflections from one or more reflective surfaces. One or more propagation pathways may pass through an RF obstacle, such as, for example, a lossy dielectric material. Each reflective surface and RF obstacle is associated with a reflection coefficient and a transmission coefficient.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: September 12, 1995
    Assignee: AT&T Corp.
    Inventors: Steven J. Fortune, David M. Gay, Brian W. Kernighan, Orlando Landron, Reinaldo A. Valenzuela, Margaret H. Wright
  • Patent number: 4577276
    Abstract: In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.
    Type: Grant
    Filed: September 12, 1983
    Date of Patent: March 18, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Alfred E. Dunlop, Brian W. Kernighan