Patents by Inventor Brian W. Messenger
Brian W. Messenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9293382Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.Type: GrantFiled: October 24, 2014Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
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Publication number: 20150041809Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Inventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
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Patent number: 8927989Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.Type: GrantFiled: November 28, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
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Publication number: 20140145191Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
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Patent number: 8723243Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.Type: GrantFiled: November 4, 2013Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20140054664Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.Type: ApplicationFiled: November 4, 2013Publication date: February 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8642423Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.Type: GrantFiled: November 30, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20130134491Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8445362Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: GrantFiled: October 11, 2006Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Publication number: 20120161855Abstract: An apparatus for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: ApplicationFiled: March 6, 2012Publication date: June 28, 2012Applicant: International Business Machines CorporationInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Patent number: 8106485Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.Type: GrantFiled: March 7, 2008Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: William G. America, Steven H. Johnston, Brian W. Messenger
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Patent number: 7757200Abstract: A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: GrantFiled: November 16, 2007Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Publication number: 20090128225Abstract: A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Publication number: 20080224273Abstract: A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.Type: ApplicationFiled: March 7, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William G. AMERICA, Steven H. Johnston, Brian W. Messenger
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Patent number: 7368393Abstract: A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.Type: GrantFiled: April 20, 2006Date of Patent: May 6, 2008Assignee: International Business Machines CorporationInventors: William G. America, Steven H. Johnston, Brian W. Messenger
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Publication number: 20080089159Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
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Patent number: 6706586Abstract: A method of fabricating a high aspect ratio deep trench having smooth sidewalls in a semiconductor substrate comprising a first etching step of contacting the substrate in which the deep trench is to be etched with either NF3 gas or SF6 gas in the absence of the other, followed by a second etching step with the etching gas of either NF3 or SF6 which ever one was not used in the first etching step, and alternating the first and second etching steps until the desired high aspect ratio trench depth is reached.Type: GrantFiled: October 23, 2002Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Christophe N. Collins, Rajarao Jammy, Brian W. Messenger, Siddhartha Panda