Patents by Inventor Brian W. Quinlan
Brian W. Quinlan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200176383Abstract: A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Inventors: Charles L. Arvin, Brian W. Quinlan, Steve Ostrander, Thomas Weiss, Mark W. Kapfhammer, Shidong Li
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Publication number: 20200161272Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Inventors: CHARLES L. ARVIN, CLEMENT J. FORTIN, CHRISTOPHER D. MUZZY, BRIAN W. QUINLAN, THOMAS A. WASSICK, THOMAS WEISS
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Patent number: 10660209Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: GrantFiled: November 14, 2017Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10622299Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: GrantFiled: February 7, 2019Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10607928Abstract: An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.Type: GrantFiled: August 1, 2019Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventors: Anson J. Call, Sushumna Iruvanti, Shidong Li, Brian W. Quinlan, Kamal K. Sikka, Rui Wang
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Patent number: 10586782Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.Type: GrantFiled: July 1, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Clement J. Fortin, Christopher D. Muzzy, Brian W. Quinlan, Thomas A. Wassick, Thomas Weiss
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Patent number: 10566275Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.Type: GrantFiled: January 15, 2019Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan
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Publication number: 20200035593Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga
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Patent number: 10515929Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: GrantFiled: April 9, 2018Date of Patent: December 24, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190378816Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312011Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: May 31, 2019Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312009Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312010Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Patent number: 10431563Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: GrantFiled: April 9, 2018Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190172784Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: ApplicationFiled: February 7, 2019Publication date: June 6, 2019Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20190148283Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.Type: ApplicationFiled: January 15, 2019Publication date: May 16, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan
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Publication number: 20190150287Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Inventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10224274Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10224273Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10224269Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.Type: GrantFiled: December 17, 2015Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan