Abstract: A TTL to CMOS translating input buffer circuit receives TTL input data signals at an input (V.sub.IN) and delivers CMOS data signals at an output (V.sub.OUT). The input buffer circuit is provided with an expanded first stage with expanded pullup circuit (P1) and pulldown circuit (N1) having control gate nodes coupled to the input (V.sub.IN). The pullup and pulldown circuits (P1,N1) are constructed to provide dual switching thresholds at the input (V.sub.IN). A first stage output pullup and pulldown circuit (P1R,P1L,N1L) switches at a relatively lower first threshold voltage level. A pullup enhancer circuit (P1E,I3,I4) switches at a relatively higher second threshold voltage level. The pullup and pulldown circuits (P1,N1) of the expanded first stage are constructed for switching dynamic current at an output node (m1) at the relatively lower first threshold voltage level for data signal transitions between high and low potential levels at the output node (m1).