Patents by Inventor Brian Walter O'Krafka

Brian Walter O'Krafka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8229945
    Abstract: A distributed database system has multiple compute nodes each running an instance of a database management system (DBMS) program that accesses database records in a local buffer cache. Records are persistently stored in distributed flash memory on multiple storage nodes. A Sharing Data Fabric (SDF) is a middleware layer between the DBMS programs and the storage nodes and has API functions called by the DBMS programs when a requested record is not present in the local buffer cache. The SDF fetches the requested record from flash memory and loads a copy into the local buffer cache. The SDF has threads on a home storage node that locate database records using a node map. A global cache directory locks and pins records to local buffer caches for updating by a node's DBMS program. DBMS operations are grouped into transactions that are committed or aborted together as a unit.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: July 24, 2012
    Assignee: Schooner Information Technology, Inc.
    Inventors: Darpan Dinker, Andrew David Eckhardt, Darryl Manabu Ouye, Brian Walter O'Krafka, Earl T. Cohen, Thomas M. McWilliams
  • Publication number: 20090240869
    Abstract: A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.
    Type: Application
    Filed: August 25, 2008
    Publication date: September 24, 2009
    Applicant: SCHOONER INFORMATION TECHNOLOGY, INC.
    Inventors: Brian Walter O'Krafka, Michael John Koster, Darpan Dinker, Earl T. Cohen, Thomas M. McWilliams
  • Publication number: 20090240664
    Abstract: A distributed database system has multiple compute nodes each running an instance of a database management system (DBMS) program that accesses database records in a local buffer cache. Records are persistently stored in distributed flash memory on multiple storage nodes. A Sharing Data Fabric (SDF) is a middleware layer between the DBMS programs and the storage nodes and has API functions called by the DBMS programs when a requested record is not present in the local buffer cache. The SDF fetches the requested record from flash memory and loads a copy into the local buffer cache. The SDF has threads on a home storage node that locate database records using a node map. A global cache directory locks and pins records to local buffer caches for updating by a node's DBMS program. DBMS operations are grouped into transactions that are committed or aborted together as a unit.
    Type: Application
    Filed: November 24, 2008
    Publication date: September 24, 2009
    Applicant: Schooner Information Technology, Inc.
    Inventors: Darpan Dinker, Andrew David Eckhardt, Darryl Manabu Ouye, Brian Walter O'Krafka, Earl T. Cohen, Thomas M. McWilliams
  • Patent number: 6285974
    Abstract: One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: September 4, 2001
    Assignee: International Business Machines Corporation
    Inventors: Sriram Mandyam, Brian Walter O'Krafka, Ramanathan Raghavan, Robert James Ramirez, Miwako Tokugawa
  • Patent number: 6021261
    Abstract: A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: February 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Archie Don Barrett, Jr., Sriram Srinivasan Mandyam, Brian Walter O'Krafka, Brett Adam St. Onge, Robert James Ramirez
  • Patent number: 5928334
    Abstract: One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Sriram Mandyam, Brian Walter O'Krafka, Ramanathan Raghavan, Robert James Ramirez, Miwako Tokugawa
  • Patent number: 5740353
    Abstract: A method and apparatus for creating a multiprocessor verification environment. A Multiprocessor Test Generator (MPTG) generates a set of test cases in a Multiprocessor Test Language (MTL) format subject to constraints and enumeration controls in a test specification. An abstract system model of the machine under test is inputted to the Multiprocessor Test Generator. The Multiprocessor Test Generator (MPTG) receives the test specification and abstract system model, accesses a system specific database and generates test cases based on the constraints in the test specification in a Multiprocessor Test Language (MTL). The Multiprocessor Test Language (MTL) test cases are inputted to a Multiprocessor Test Executive (MPX) which controls the issuance of the test cases to a cache-coherent multiprocessor system, and monitors their completion in order to verify operation of the cache-coherent multiprocessor system.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: April 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Thomas Kreulen, Sriram Srinivasan Mandyam, Brian Walter O'Krafka, Shahram Salamian, Ramanathan Raghavan