Patents by Inventor Brian William Condie

Brian William Condie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230019230
    Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Sung Chul Joo, Alexander Komposch, Brian William Condie, Benjamin Law, Jae Hyung Jeremiah Park
  • Patent number: 11488923
    Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 1, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Sung Chul Joo, Alexander Komposch, Brian William Condie, Benjamin Law, Jae Hyung Jeremiah Park
  • Publication number: 20200373270
    Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Sung Chul Joo, Alexander Komposch, Brian William Condie, Benjamin Law, Jae Hyung Jeremiah Park
  • Patent number: 9373577
    Abstract: A semiconductor package includes a substrate, an RF semiconductor die attached to a first side of the substrate, a capacitor attached to the first side of the substrate, and a first terminal on the first side of the substrate. The semiconductor package further includes copper or aluminum bonding wires or ribbons connecting the first terminal to an output of the RF semiconductor die, and gold bonding wires or ribbons connecting the capacitor to the output of the RF semiconductor die. The gold bonding wires or ribbons are designed to accommodate greater RF Joule heating during operation of the RF semiconductor die than the copper or aluminum bonding wires or ribbons. Corresponding methods of manufacturing are also described.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Alexander Komposch, Brian William Condie, Erwin Orejola, Michael Real
  • Publication number: 20140346637
    Abstract: A semiconductor package includes a substrate, an RF semiconductor die attached to a first side of the substrate, a capacitor attached to the first side of the substrate, and a first terminal on the first side of the substrate. The semiconductor package further includes copper or aluminum bonding wires or ribbons connecting the first terminal to an output of the RF semiconductor die, and gold bonding wires or ribbons connecting the capacitor to the output of the RF semiconductor die. The gold bonding wires or ribbons are designed to accommodate greater RF Joule heating during operation of the RF semiconductor die than the copper or aluminum bonding wires or ribbons. Corresponding methods of manufacturing are also described.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Inventors: Alexander Komposch, Brian William Condie, Erwin Orejola, Michael Real