Patents by Inventor Brian William Hughes

Brian William Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190218873
    Abstract: In composite slips and downhole tools using composite slips, there are provided one or more slip segments. The slip segments comprise a body and one or more inserts. The body is a composite material having an outer surface. The inserts each have an upper surface and each of the inserts is mechanically affixed into the body such that the upper surface of each of the inserts extends at least partially out from the outer surface. In some embodiments, the inserts are oval or stadium shaped and have a shoulder that locks the insert from moving by interaction with a shoulder in a cavity wall of the body.
    Type: Application
    Filed: October 19, 2016
    Publication date: July 18, 2019
    Inventors: Kyle Wayne Davis, Gregory William Vargus, Daniel F. Funk, Brian Heath Hughes, Joel Barlow
  • Patent number: 8924662
    Abstract: A method for controlling data flow to a pair of storage devices includes receiving at least one new entry to store in a first storage device or a second storage device in the pair of storage devices and determining a number of entries made to the first and second storage devices out of the at least one new entry. The method also includes calculating a difference between available space in the first storage device and the second storage device, and calculating a number of credits used by the at least one new entry based on the numbers of entries to the first and second storage devices and on the difference in available space.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: December 30, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Brian William Hughes
  • Patent number: 8560925
    Abstract: A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 15, 2013
    Assignees: DENSO International America, Inc., Denso Corporation
    Inventors: Brian William Hughes, Hiroaki Shibata, Wan-ping Yang
  • Publication number: 20120260148
    Abstract: A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicants: DENSO CORPORATION, DENSO INTERNATIONAL AMERICA, INC.
    Inventors: Brian William Hughes, Hiroaki Shibata, Wan-Ping Yang
  • Publication number: 20080189504
    Abstract: A method for controlling data flow to a pair of storage devices includes receiving at least one new entry to store in a first storage device or a second storage device in the pair of storage devices and determining a number of entries made to the first and second storage devices out of the at least one new entry. The method also includes calculating a difference between available space in the first storage device and the second storage device, and calculating a number of credits used by the at least one new entry based on the numbers of entries to the first and second storage devices and on the difference in available space.
    Type: Application
    Filed: April 9, 2008
    Publication date: August 7, 2008
    Inventor: Brian William Hughes
  • Patent number: 7380080
    Abstract: A method for controlling data flow to a pair of storage devices includes receiving at least one new entry to store in a first storage device or a second storage device in the pair of storage devices and determining a number of entries made to the first and second storage devices out of the at least one new entry. The method also includes calculating a difference between available space in the first storage device and the second storage device, and calculating a number of credits used by the at least one new entry based on the numbers of entries to the first and second storage devices and on the difference in available space.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 27, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Brian William Hughes
  • Patent number: 7373467
    Abstract: A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and assembling the plurality of data sources in a prioritized list. The method also includes removing lowest priority data sources one by one from the prioritized list until a total of the requests made by all data sources remaining in the prioritized list are within a number of available data write credits, and granting the requests for all the data sources remaining in the prioritized list.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 13, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Brian William Hughes
  • Patent number: 7055074
    Abstract: The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: May 30, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Brian William Hughes, J. Michael Hill, Warren Kurt Howlett
  • Patent number: 6691252
    Abstract: The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: February 10, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Brian William Hughes, Warren Kurt Howlett
  • Publication number: 20020184557
    Abstract: The present invention is directed to a system and method of evaluating the reliability of a memory segment wherein this method comprises the steps of counting malfunctioning elements in at least one instance of a defined geometric pattern of the memory segment, declaring a fault condition within the memory segment if a number of counted malfunctioning elements at least equals a fault threshold, and re-mapping the memory segment in response to a declared fault condition.
    Type: Application
    Filed: April 25, 2001
    Publication date: December 5, 2002
    Inventors: Brian William Hughes, J. Michael Hill, Warren Kurt Howlett
  • Publication number: 20020162062
    Abstract: The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.
    Type: Application
    Filed: April 25, 2001
    Publication date: October 31, 2002
    Inventors: Brian William Hughes, J. Michael Hill, Warren Kurt Howlett
  • Publication number: 20020120887
    Abstract: The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.
    Type: Application
    Filed: February 23, 2001
    Publication date: August 29, 2002
    Inventors: Brian William Hughes, Warren Kurt Howlett
  • Publication number: 20020108073
    Abstract: The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is operational. Non-operational cells are replaced by first replacing columns which contain a number of non-operational cells with spare columns and second removing any remaining non-operational cells by replacing the rows containing those non-operational cells with spare rows.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 8, 2002
    Inventor: Brian William Hughes
  • Patent number: 6373758
    Abstract: The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is operational. Non-operational cells are replaced by first replacing columns which contain a threshold number of non-operational cells with spare columns and second removing any remaining non-operational cells by replacing the rows containing those non-operational cells with spare rows.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: April 16, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Brian William Hughes, Warren Kurt Howlett