Abstract: A system includes an encoder to monitor a machine and generate an encoder output signal indicative of at least one of the motion or position of the machine. A combiner can be configured to receive the encoder output signal from the encoder and to receive machine diagnostic data from at least one other sensor. The combiner can combine the machine diagnostic data with the encoder output signal to provide a combined signal that includes the machine diagnostic data synchronized with the at least one of the motion or position of the machine. An output stage can provide the combined signal to a remote system.

Abstract: A system includes an encoder to monitor a machine and generate an encoder output signal indicative of at least one of the motion or position of the machine. A combiner can be configured to receive the encoder output signal from the encoder and to receive machine diagnostic data from at least one other sensor. The combiner can combine the machine diagnostic data with the encoder output signal to provide a combined signal that includes the machine diagnostic data synchronized with the at least one of the motion or position of the machine. An output stage can provide the combined signal to a remote system.

Abstract: A surfing pipelined logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.

Abstract: A surfing pipelined logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.