Patents by Inventor Brian Winters

Brian Winters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Surfing logic pipelines
    Patent number: 6768342
    Abstract: A surfing pipelined logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: July 27, 2004
    Assignee: University of British Columbia
    Inventors: Mark Greenstreet, Brian Winters
  • Surfing logic pipelines
    Publication number: 20030076131
    Abstract: A surfing pipelined logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 24, 2003
    Inventors: Mark Greenstreet, Brian Winters