Patents by Inventor Brice De Jaeger
Brice De Jaeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114537Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.Type: GrantFiled: January 21, 2020Date of Patent: September 7, 2021Assignee: IMEC VZWInventors: Steve Stoffels, Niels Posthuma, Brice De Jaeger
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Publication number: 20200235218Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.Type: ApplicationFiled: January 21, 2020Publication date: July 23, 2020Inventors: Steve Stoffels, Niels Posthuma, Brice De Jaeger
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Patent number: 9728629Abstract: An electronic device can include a substrate having a primary surface; a monocrystalline semiconductor film overlying the primary surface of the substrate; and a polycrystalline compound semiconductor layer adjacent to the monocrystalline semiconductor film. In an embodiment, the polycrystalline compound semiconductor layer has a dopant concentration at most 1×1016 atoms/cm3, a donor concentration of greater than 1×1017 donors/cm3, and is part of a contact of an electrode of a transistor. In another embodiment, the electronic device can further include an interconnect over the polycrystalline compound semiconductor layer, wherein a combination of the interconnect and polycrystalline compound semiconductor layer form an ohmic contact. In a further embodiment, a polycrystalline compound semiconductor layer can be adjacent to the monocrystalline semiconductor film, wherein an energy level of a conduction band of the polycrystalline compound semiconductor layer is lower than its Fermi energy level.Type: GrantFiled: July 14, 2016Date of Patent: August 8, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Abhishek Banerjee, Aurore Constant, Peter Moens, Brice De Jaeger
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Patent number: 9698309Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.Type: GrantFiled: January 6, 2016Date of Patent: July 4, 2017Assignee: IMEC VZWInventors: Celso Cavaco, Brice De Jaeger, Marleen Van Hove, Vasyl Motsnyi
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Patent number: 9634107Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.Type: GrantFiled: May 22, 2014Date of Patent: April 25, 2017Assignee: IMECInventors: Brice De Jaeger, Marleen Van Hove, Stefaan Decoutere, Steve Stoffels
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Publication number: 20160118542Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Applicant: IMEC VZWInventors: Celso Cavaco, Brice De Jaeger, Marleen Van Hove, Vasyl Motsnyi
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Publication number: 20150162212Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.Type: ApplicationFiled: November 24, 2014Publication date: June 11, 2015Applicant: IMEC VZWInventors: Celso Cavaco, Brice De Jaeger, Marleen Van Hove, Vasyl Motsnyi
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Publication number: 20140346568Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.Type: ApplicationFiled: May 22, 2014Publication date: November 27, 2014Applicant: IMECInventors: Brice De Jaeger, Marleen Van Hove, Stefaan Decoutere
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Patent number: 8207030Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si nMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si nMOS can be lowered to be compatible with Ge pMOS.Type: GrantFiled: April 28, 2009Date of Patent: June 26, 2012Assignee: IMECInventors: David Paul Brunco, Brice De Jaeger, Simone Severi
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Publication number: 20090272976Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS.Type: ApplicationFiled: April 28, 2009Publication date: November 5, 2009Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: David Paul Brunco, Brice De Jaeger, Simone Severi
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Patent number: 7517765Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.Type: GrantFiled: September 8, 2006Date of Patent: April 14, 2009Assignees: Interuniversitair Microelektronica Centrum (IMEC), Intel Corporation (INTEL), Katholieke Universiteit Leuven (KUL)Inventors: David P. Brunco, Karl Opsomer, Brice De Jaeger
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Publication number: 20070032025Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.Type: ApplicationFiled: September 8, 2006Publication date: February 8, 2007Applicants: Interuniversitair Microelektronica Centrum (IMEC), Intel Corporation (INTEL), Katholieke Universiteit Leuven (KUL)Inventors: David Brunco, Karl Opsomer, Brice De Jaeger